Patents by Inventor Sandeep Ahuja

Sandeep Ahuja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194332
    Abstract: A microelectronic device may include a substrate, a first component, a second component, a slug, a heat spreader, and a heatsink. The substrate may include a plurality of electrically conductive elements. The first component may be coupled to the substrate. The second component may be coupled to the substrate. The slug may be thermally coupled to the second component. The heat spreader may be in contact with the substrate, where the heat spreader may be thermally coupled to the first component. The heatsink may be thermally coupled to the heat spreader and the slug.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 18, 2020
    Inventors: Sandeep Ahuja, Je-young Chang, Phil Geng, Shrenik Kothari, Francisco Gabriel Lozano Sanchez
  • Patent number: 10667438
    Abstract: A method for determining whether to perform maintenance for an electronic device includes generating a baseline characterization of thermal performance for a heat-generating component of the electronic device at a baseline date. The method also includes generating an assessment characterization of the thermal performance at an assessment date after the baseline date. The method further includes generating a historical trend that includes the baseline characterization and the assessment characterization. Additionally, the method includes determining whether to perform maintenance for the heat-generating component based on the historical trend and a specified maintenance parameter.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Robin A. Steinbrecher, Nishi Ahuja, Sandeep Ahuja
  • Publication number: 20190204885
    Abstract: In one embodiment, a processor comprises: a first die including at least one core and at least one first die thermal sensor; a second die including at least one memory and at least one second die thermal sensor; and a thermal controller to receive first thermal data from the at least one first die thermal sensor and second thermal data from the at least one second die thermal sensor, calculate a first thermal margin for the first die based at least in part on the first thermal data and a first thermal loadline for the first die and calculate a second thermal margin for the second die based at least in part on the second thermal data and a second thermal loadline for the second die. Other embodiments are described and claimed.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 4, 2019
    Inventors: Sandeep Ahuja, Jeremy Ridge, Michael Berktold
  • Patent number: 10275001
    Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Timothy Y. Kam, Sandeep Ahuja, Rajat Agarwal, Avinash Sodani, Jinho Suh, Meenakshisundaram Chinthamani
  • Patent number: 10248173
    Abstract: In one embodiment, a processor comprises: a first die including at least one core and at least one first die thermal sensor; a second die including at least one memory and at least one second die thermal sensor; and a thermal controller to receive first thermal data from the at least one first die thermal sensor and second thermal data from the at least one second die thermal sensor, calculate a first thermal margin for the first die based at least in part on the first thermal data and a first thermal loadline for the first die and calculate a second thermal margin for the second die based at least in part on the second thermal data and a second thermal loadline for the second die. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Jeremy Ridge, Michael Berktold
  • Publication number: 20190041925
    Abstract: In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 7, 2019
    Inventors: Sandeep Ahuja, Nikhil Gupta, Vasudevan Srinivasan
  • Publication number: 20180270993
    Abstract: Embodiments described herein may include apparatuses, systems and/or processes to provide an evaporator including a chamber to receive condensate flow from an input end and output a vapor outflow at an output end with a wick, heated by a surface of the chamber, having variable thickness within the chamber to receive condensate, where the thickness of the wick proximate to the condensate inflow is greater than the thickness of the wick proximate to the vapor outflow. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 20, 2018
    Inventors: Devdatta P. Kulkarni, Sandeep Ahuja
  • Publication number: 20180252483
    Abstract: Apparatus and method to increase structural integrity of heatsinks are described herein. In embodiments, an apparatus may include a plurality of thermal dissipation fins; and a base disposed below the plurality of thermal dissipation fins, wherein the base is to include an evacuated space in which one or more thermal transport pipes and one or more stiffener structures are disposed, the evacuated space is to include a first side proximate to the plurality of thermal dissipation fins and a second side opposite the first side, and wherein a stiffener structure of the one or more stiffener structures attaches to the first or second side.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Inventors: Phil Geng, Tejinder Pal S. Aulakh, Sandeep Ahuja
  • Patent number: 9971890
    Abstract: Methods and systems may provide for identifying a thermal management setting in a computing system, and comparing the thermal management setting to valid configuration information. In addition, the thermal management setting may be modified if it does not comply with the valid configuration information, wherein the modification can cause the thermal management setting to comply with the valid configuration information. Additionally, a threat risk notification can be initiated in order to notify users of the non-compliance.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Robin Steinbrecher, David Richardson
  • Publication number: 20170285699
    Abstract: In one embodiment, a processor comprises: a first die including at least one core and at least one first die thermal sensor; a second die including at least one memory and at least one second die thermal sensor; and a thermal controller to receive first thermal data from the at least one first die thermal sensor and second thermal data from the at least one second die thermal sensor, calculate a first thermal margin for the first die based at least in part on the first thermal data and a first thermal loadline for the first die and calculate a second thermal margin for the second die based at least in part on the second thermal data and a second thermal loadline for the second die. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Sandeep Ahuja, Jeremy Ridge, Michael Berktold
  • Patent number: 9646910
    Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Eric W. Buddrius, Roger D. Flynn, Rajat Agarwal
  • Publication number: 20160378149
    Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Timothy Y. Kam, Sandeep Ahuja, Rajat Agarwal, Avinash Sodani, Jinho Suh, Meenakshisundaram Chinthamani
  • Patent number: 9494996
    Abstract: A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Robin A. Steinbrecher, Susan F. Smith, Sandeep Ahuja, Vivek Garg, Tessil Thomas, Krishnakanth V. Sistla, Chris Poirier, Martin Mark T. Rowland
  • Publication number: 20160267269
    Abstract: Methods and systems may provide for identifying a thermal management setting in a computing system, and comparing the thermal management setting to valid configuration information. In addition, the thermal management setting may be modified if it does not comply with the valid configuration information, wherein the modification can cause the thermal management setting to comply with the valid configuration information. Additionally, a threat risk notification can be initiated in order to notify users of the non-compliance.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventors: Sandeep Ahuja, Robin Steinbrecher, David Richardson
  • Publication number: 20160179158
    Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
    Type: Application
    Filed: September 14, 2015
    Publication date: June 23, 2016
    Inventors: Tessil Thomas, Robin A. Steinbrecher, Sandeep Ahuja, Michael Berktold, Timothy Y. Kam, Howard Chin, Phani Kumar Kandula, Krishnakanth V. Sistla
  • Publication number: 20160155682
    Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 2, 2016
    Inventors: Sandeep Ahuja, Eric W. Buddrius, Roger D. Flynn, Rajat Agarwal
  • Patent number: 9355249
    Abstract: Methods and systems may provide for identifying a thermal management setting in a computing system, and comparing the thermal management setting to valid configuration information. In addition, the thermal management setting may be modified if it does not comply with the valid configuration information, wherein the modification can cause the thermal management setting to comply with the valid configuration information. Additionally, a threat risk notification can be initiated in order to notify users of the non-compliance.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Robin Steinbrecher, David Richardson
  • Patent number: 9257364
    Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Eric W. Buddrius, Roger D. Flynn, Rajat Agarwal
  • Patent number: 9142482
    Abstract: Thermal management systems for semiconductor devices are provided. Embodiments of the invention provide two or more liquid cooling subsystems that are each capable of providing active cooling to one or more semiconductor devices, such as packaged processors. In operation, a first liquid cooling subsystem can provide active cooling to the semiconductor device(s) while the second cooling subsystem is circulating a heat transfer fluid within its own subsystem. The second liquid cooling subsystem can be then switched into operation and provides active cooling to the semiconductor device(s) while the first cooling subsystem is circulating heat transfer fluid within its own subsystem. In alternate embodiments, the heat transfer fluid remains in the subsystem, but does not circulate within the subsystem when the subsystem is not providing cooling to the semiconductor device(s). The subsystems comprise heat dissipation units.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Ioan Sauciuc, Susan F. Smith
  • Patent number: 9116050
    Abstract: An apparatus may include an integrated circuit die having a plurality of temperature sensors and a control unit integrated thereon. The control unit can calculate an average die temperature based on readings from the plurality of temperature sensors, compare the average die temperature to a specification temperature and control an off-die cooling system based on the comparison.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 25, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Robin A. Steinbrecher, Susan F. Smith, David J. Ayers