Patents by Inventor Sandeep Gaan

Sandeep Gaan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200245472
    Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2017
    Publication date: July 30, 2020
    Inventors: Darko GRUJICIC, Rengarajan SHANMUGAM, Sandeep GAAN, Adrian BAYRAKTAROGLU, Roy DITTLER, Ke LIU, Suddhasattwa NAD, Marcel A. WALL, Rahul N. MANEPALLI, Ravindra V. TANIKELLA
  • Publication number: 20200051899
    Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Debendra MALLIK, Sanka GANESAN, Pilin LIU, Shawna LIFF, Sri Chaitra CHAVALI, Sandeep GAAN, Jimin YAO, Aastha UPPAL
  • Publication number: 20190279806
    Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Inventors: Kristof DARMAWIKARTA, Srinivas PIETAMBARAM, Sandeep GAAN, Sri Ranga Sai BOYAPATI, Prithwish CHATTERJEE, Sameer PAITAL, Rahul JAIN, Junnan ZHAO
  • Publication number: 20190259631
    Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: August 22, 2019
    Inventors: Robert Alan MAY, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati, Sandeep Gaan, Srinivas V. Pietambaram
  • Publication number: 20190206786
    Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Sandeep GAAN, Srinivas V. PIETAMBARAM, Sameer R. PAITAL
  • Publication number: 20190006457
    Abstract: A semiconductor device may include a plurality of layers of a substrate. A die may be coupled to at least one of the plurality of layers of the substrate. A passive electrical component may be integrally formed within the layers of the substrate. The passive electrical component may be a resistor or a capacitor. One or more conductors may be configured to allow electrical communication between the passive electrical component and the die. The one or more conductors may be integrally formed within the plurality of layers of the substrate.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Aleksandar Aleksov, Kristof Darmawikarta, Robert Alan May, Sandeep Gaan
  • Publication number: 20180040505
    Abstract: A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide layer is formed in the trench. A diffusionless anneal process is performed to densify the first oxide layer. The first oxide layer is recessed to define a recess. A second oxide layer is formed in the recess.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Sandeep Gaan, Shishir Ray, Vikrant Chauhan
  • Patent number: 9831098
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xinyuan Dou, Sukwon Hong, Satyajit Shinde, Sandeep Gaan, Tao Han, Carlos Chacon, Shimpei Yamaguchi
  • Patent number: 9673039
    Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Yiqun Liu, Jin Ping Liu, Fabio D'Addamio, Sandeep Gaan
  • Patent number: 9570291
    Abstract: Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Shishir Ray, Sandeep Gaan, Sheldon Meyers, Nisha Pillai, Edmund Kenneth Banghart, Kyle Jung
  • Publication number: 20170018452
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.
    Type: Application
    Filed: July 13, 2015
    Publication date: January 19, 2017
    Inventors: Xinyuan Dou, Sukwon Hong, Satyajit Shinde, Sandeep Gaan, Tao Han, Carlos Chacon, Shimpei Yamaguchi
  • Publication number: 20170018426
    Abstract: Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Shishir Ray, Sandeep Gaan, Sheldon Meyers, Nisha Pillai, Edmund Kenneth Banghart, Kyle Jung
  • Patent number: 9520395
    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
  • Patent number: 9502232
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Huang Liu, Adam Selsley
  • Patent number: 9466701
    Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Sandeep Gaan, Sipeng Gu
  • Publication number: 20160284540
    Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 29, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shishir RAY, Yiqun LIU, Jin Ping LIU, Fabio D'ADDAMIO, Sandeep GAAN
  • Patent number: 9385192
    Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
  • Publication number: 20160079242
    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: GUILLAUME BOUCHE, Andy Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
  • Publication number: 20160005598
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng GU, Sandeep GAAN, Zhiguo SUN, Huang LIU, Adam SELSLEY
  • Patent number: 9224842
    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan