Patents by Inventor Sandeep Gaan
Sandeep Gaan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9502232Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.Type: GrantFiled: July 2, 2014Date of Patent: November 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Huang Liu, Adam Selsley
-
Patent number: 9466701Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.Type: GrantFiled: April 3, 2014Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Sandeep Gaan, Sipeng Gu
-
Publication number: 20160284540Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Shishir RAY, Yiqun LIU, Jin Ping LIU, Fabio D'ADDAMIO, Sandeep GAAN
-
Patent number: 9385192Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: GrantFiled: July 27, 2015Date of Patent: July 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
-
Publication number: 20160079242Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.Type: ApplicationFiled: November 23, 2015Publication date: March 17, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: GUILLAUME BOUCHE, Andy Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
-
Publication number: 20160005598Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Sipeng GU, Sandeep GAAN, Zhiguo SUN, Huang LIU, Adam SELSLEY
-
Patent number: 9224842Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.Type: GrantFiled: April 22, 2014Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
-
Publication number: 20150333121Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
-
Patent number: 9184288Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.Type: GrantFiled: March 13, 2014Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Zhiguo Sun, Sandeep Gaan, Danni Chen, Wen-Pin Peng, Huang Liu
-
Publication number: 20150303273Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.Type: ApplicationFiled: April 22, 2014Publication date: October 22, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
-
Publication number: 20150287795Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.Type: ApplicationFiled: April 3, 2014Publication date: October 8, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Sandeep Gaan, Sipeng Gu
-
Publication number: 20150263169Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Sipeng GU, Zhiguo SUN, Sandeep GAAN, Danni CHEN, Wen-Pin PENG, Huang LIU
-
Patent number: 9123771Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: GrantFiled: February 13, 2013Date of Patent: September 1, 2015Assignee: GlobalFoundries Inc.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
-
Patent number: 9076645Abstract: Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.Type: GrantFiled: May 8, 2014Date of Patent: July 7, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Shishir Ray, Sandeep Gaan, Jin Ping Liu, Zhiguo Sun
-
Patent number: 8940650Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.Type: GrantFiled: March 6, 2013Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan
-
Publication number: 20140256141Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan
-
Publication number: 20140227858Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: ApplicationFiled: February 13, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim