Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using the regulatory elements, including the promoters and/or 3?-UTRs, isolated from Brachypodium distachyon ubiquitin genes.

Abstract: This disclosure provides an extended-release capsule dosage form of metoprolol succinate in the form of coated discrete units, wherein said capsule dosage form is bioequivalent to the marketed Toprol-XL® tablet. The extended-release capsule dosage form comprising coated discrete units can be sprinkled onto food to ease administration to patients who have difficulty swallowing tablets or capsules.

Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

Abstract: This disclosure provides an extended-release capsule dosage form of metoprolol succinate in the form of coated discrete units, wherein said capsule dosage form is bioequivalent to the marketed Toprol-XL® tablet. The extended-release capsule dosage form comprising coated discrete units can be sprinkled onto food to ease administration to patients who have difficulty swallowing tablets or capsules.

Abstract: An apparatus and method for tracking content are provided. The apparatus is an electronic device that includes a communication circuit and a processor electrically connected to the communication circuit. The processor may be configured to receive information about a tracking target item from an external electronic device, to receive content from a content provider, determine a degree of semantic similarity between the tracking target item and the content, generate at least one update related to the tracking target item, based on the degree of semantic similarity, and send the at least one update to the external electronic device.

Abstract: Provided are methods, vectors and gene constructs for enhancing expression of a recombinant nucleic acid sequence in transgenic plants and plant tissues. According to the present invention, nucleic acid sequences are obtained and/or derived from the 3? untranslated regions of genes encoding ubiquitin proteins and engineered to flank respective portions of a selected coding region of a vector. The vector construct may be introduced into plants and/or plant tissues through conventional or gene targeting procedures, resulting in enhanced expression of the selected coding region. In some embodiments, the selected coding region is a chimeric gene or gene fragment expressing one or more proteins known to impart a level of insecticidal activity to a transgenic plant and/or plant tissue.

Abstract: An embodiment is method comprising attaching a first die and a second die to a first surface of a first interposer using respective ones of first conductive connectors coupled to respective first surfaces of the first die and the second die; attaching a third die and a fourth die to a second surface of the first interposer using respective ones of second conductive connectors, the second surface of the first interposer being opposite the first surface of the interposer; and attaching the first die and the second die to a substrate using respective ones of third conductive connectors coupled to respective second surfaces of the first die and the second die.

Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.

Abstract: The presently disclosed subject matter is directed to a method of processing plant oil to produce high grade fuel such as biodiesel and jet fuel. Particularly, a method is provided that includes treating an oil under hydrothermal conditions in the presence of i) an acid that acts as an in situ source of hydrogen and ii) an activated carbon essentially free of a metal catalyst, wherein the treating results in production of liquid hydrocarbons for use as a fuel.

Abstract: A differential includes a differential case; a side gear; a pinion configured for meshing engagement with the side gear; and a pinion housing configured to support the pinion. The pinion housing includes a first face; a second face opposing the first face; a first projection located on the first face; and a second projection located on the second face. The pinion housing also includes an aperture or hole extending radially inwardly from an outer radial surface of the generally annular ring; and a channel extending from the first face to the second face, wherein the channel is substantially radially aligned with the aperture or hole. In embodiments, the pinion housing includes one or more transfer formations configured to transfer torque from the differential case, and the pinion housing is configured to permit movement in an axial direction between a pair of side gears.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using Zea mays GRMZM2G015295 gene regulatory elements.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using the regulatory elements, including the promoters and/or 3?-UTRs, isolated from Panicum virgatum ubiquitin genes.

Abstract: A method of detecting one or more faults in a semiconductor device that includes generating one or more secondary node lists from a primary node list. The primary node list includes one or more nodes. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists. The method also includes generating a test pattern set from the secondary node list and a fault list. The fault list identifies one or more faults.

Abstract: A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type.

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

Abstract: Provided is a system that includes a monitoring unit, processing units, and peripheral units. Each of the processing units is linked to the monitoring unit and each of the peripheral units is also linked to the monitoring unit. Each of the processing units is configured to transmit requests to and subsequently receive responses from at least one of the peripheral units through the monitoring unit. The monitoring unit is configured to measure and store delays between the responses and the respective requests.

Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.

Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.