Patents by Inventor Sandeep Oswal
Sandeep Oswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10573292Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.Type: GrantFiled: October 13, 2017Date of Patent: February 25, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ravikumar Pattipaka, Vajeed Nimran, Sandeep Oswal
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Publication number: 20180262169Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
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Publication number: 20180137853Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.Type: ApplicationFiled: October 13, 2017Publication date: May 17, 2018Inventors: Ravikumar PATTIPAKA, Vajeed NIMRAN, Sandeep OSWAL
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Patent number: 9684066Abstract: Samples of a light radar (“LIDAR”) return signal are stored in an analog circular buffer following the transmission of a LIDAR pulse. Sampling continues for a fixed period of time or number of samples during a post-trigger sampling period after the occurrence of a trigger signal from a trigger circuit. The trigger circuit indicates the receipt of a return pulse associated with a target object based upon one or more return signal characteristics. Following the post-trigger sampling period, the stored analog samples are sequentially read out and converted to digital sample values. The digital sample values may be analyzed in a digital processor to further confirm the validity of the returned LIDAR pulse, to determine a time of arrival of the LIDAR pulse, and to calculate a distance to the target object. Some versions include multiple circular buffers and capture clocks, enabling the capture of samples from multiple return pulses.Type: GrantFiled: October 20, 2014Date of Patent: June 20, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eduardo Bartolome, Fernando Alberto Mujica, Sandeep Oswal, Abhaya Kumar
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Patent number: 9240814Abstract: In certain embodiments, systems for receiving one or more echoes are provided. The system comprises a first attenuator, a first amplifier, and a second attenuator. The first attenuator is configured to receive the one or more echo signals, and generate a corresponding set of first attenuated echo signals, respectively, based on a number of signal strengths of the one or more echo signals. The first amplifier is configured to receive and amplify the set of first attenuated echo signals to thereby generate a set of first amplified echo signals corresponding to the one or more first attenuated echo signals, respectively. The second attenuator is configured to receive the set of first amplified echo signals and generate a set of second attenuated echo signals corresponding to the set of first amplified echo signals, respectively, based on a number of signal strengths of the set of first amplified echo signals, respectively.Type: GrantFiled: March 27, 2012Date of Patent: January 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shabbir Amjhera Wala, Shagun Dusad, Sandeep Oswal, Vajeed Nimran
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Publication number: 20150280662Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.Type: ApplicationFiled: March 3, 2015Publication date: October 1, 2015Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
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Publication number: 20150116695Abstract: Samples of a light radar (“LIDAR”) return signal are stored in an analog circular buffer following the transmission of a LIDAR pulse. Sampling continues for a fixed period of time or number of samples during a post-trigger sampling period after the occurrence of a trigger signal from a trigger circuit. The trigger circuit indicates the receipt of a return pulse associated with a target object based upon one or more return signal characteristics. Following the post-trigger sampling period, the stored analog samples are sequentially read out and converted to digital sample values. The digital sample values may be analyzed in a digital processor to further confirm the validity of the returned LIDAR pulse, to determine a time of arrival of the LIDAR pulse, and to calculate a distance to the target object. Some versions include multiple circular buffers and capture clocks, enabling the capture of samples from multiple return pulses.Type: ApplicationFiled: October 20, 2014Publication date: April 30, 2015Inventors: Eduardo Bartolome, Fernando Alberto Mujica, Sandeep Oswal, Abhaya Kumar
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Patent number: 8920326Abstract: A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square.Type: GrantFiled: August 12, 2011Date of Patent: December 30, 2014Assignee: Texas Instruments IncorporatedInventors: Vajeed Nimran P A, Shabbir Amjhera Wala, Shagun Dusad, Sandeep Oswal, Visvesvaraya Appala Pentakota
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Publication number: 20130258812Abstract: In certain embodiments, systems for receiving one or more echoes are provided. The system comprises a first attenuator, a first amplifier, and a second attenuator. The first attenuator is configured to receive the one or more echo signals, and generate a corresponding set of first attenuated echo signals, respectively, based on a number of signal strengths of the one or more echo signals. The first amplifier is configured to receive and amplify the set of first attenuated echo signals to thereby generate a set of first amplified echo signals corresponding to the one or more first attenuated echo signals, respectively. The second attenuator is configured to receive the set of first amplified echo signals and generate a set of second attenuated echo signals corresponding to the set of first amplified echo signals, respectively, based on a number of signal strengths of the set of first amplified echo signals, respectively.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: Texas Instruments IncorporatedInventors: Shabbir Amjhera Wala, Shagun Dusad, Sandeep Oswal, Vajeed Nimran
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Publication number: 20130039151Abstract: A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Vajeed Nimran P. A., Shabbir Amjhera Wala, Shagun Dusad, Sandeep Oswal, Visvesvaraya Appala Pentakota
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Patent number: 8203383Abstract: A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor.Type: GrantFiled: November 23, 2009Date of Patent: June 19, 2012Assignee: Texas Instruments IncorporatedInventors: Sandeep Oswal, Neetin Agrawal
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Patent number: 7911256Abstract: A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter.Type: GrantFiled: August 14, 2009Date of Patent: March 22, 2011Assignee: Texas Instruments IncorporatedInventors: Jagannathan Venkataraman, Vajeed Nimran, Sandeep Oswal, Visveswaraya Pentakota
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Patent number: 7884746Abstract: Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.Type: GrantFiled: April 13, 2009Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Sandeep Oswal, Jagannathan Venkataraman
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Patent number: 7885144Abstract: An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.Type: GrantFiled: September 30, 2008Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Sandeep Oswal, Jagannathan Venkataraman, Visvesvaraya Appala Pentakota, Shagun Dusad
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Publication number: 20100156389Abstract: A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor.Type: ApplicationFiled: November 23, 2009Publication date: June 24, 2010Applicant: Texas Instruments IncorporatedInventors: Sandeep Oswal, Neetin Agrawal
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Publication number: 20100080083Abstract: An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sandeep Oswal, Jagannathan Venkataraman, Visvesvaraya Appala Pentakota, Shagun Dusad
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Publication number: 20100052741Abstract: A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter.Type: ApplicationFiled: August 14, 2009Publication date: March 4, 2010Applicant: Texas Instruments IncorporatedInventors: Jagannathan VENKATARAMAN, Vajeed Nimran, Sandeep Oswal, Visveswaraya Pentakota
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Publication number: 20090257558Abstract: Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.Type: ApplicationFiled: April 13, 2009Publication date: October 15, 2009Inventors: Sandeep Oswal, Jagannathan Venkataraman
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Patent number: 7576668Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.Type: GrantFiled: November 2, 2007Date of Patent: August 18, 2009Assignee: Texas Instruments IncorporatedInventors: Anand Hariraj Udupa, Vikas Kumar Sinha, Nitin Agarwal, Visvesvararaya A. Pentakota, Sandeep Oswal
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Publication number: 20080055129Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.Type: ApplicationFiled: November 2, 2007Publication date: March 6, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Udupa, Vikas Sinha, Nitin Agarwal, Visvesvararaya Pentakota, Sandeep Oswal