Patents by Inventor Sandeep Pendharkar

Sandeep Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11895530
    Abstract: A system and method for switching one or more User Equipment (UEs) 116A-N from a unicast mode to a broadcast or multicast mode to transmit a streaming media content to the UEs 116A-N is provided. The system includes, an Over-the-top (OTT) platform 104, a CDN 112, the UEs 116A-N, a cellular core network 202, one-to-many offload core 204, an analytics engine 206, a database 208, one-to-many transmitter 210, a real time switching module 212, a Cellular base station 214 and a user specified rules module 222. The analytics engine 206 continuously analyzes real-time and historical data stored in the database 208 to identify the UEs 116A-N that receive a streaming media content through the unicast mode and the streaming media content to be offloaded. An offload is a process by which certain portions of the streaming media content is shifted from the unicast mode to the broadcast or multicast mode.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 6, 2024
    Assignee: SAANKHYA LABS PVT. LTD.
    Inventors: Parag Naik, Anindya Saha, Arindam Chakraborty, Preetham Uthaiah, Sandeep Pendharkar, Yogesh Singh, Deepak Samaga
  • Publication number: 20230057887
    Abstract: A virtual Radio Access Network (vRAN) system (300) for provisioning a virtual Radio Access Network (RAN) that is portable across one or more RAN hardware platforms is provided. The virtual Radio Access Network (vRAN) system (300) includes a waveform development kit (WDK) (302), and a waveform execution environment (304). The waveform development kit (302) defines at least one portable Radio Access Network (RAN) application into a form that is instantiated on a RAN hardware (326). The waveform execution environment (304) (i) monitors real-time schedulable resources in real-time, and (ii) collects one or more statistics and monitors the one or more statistics for network automation. The waveform execution environment (304) includes a RAN hypervisor (314) that virtualizes at least one attribute of a spectral resource required to provision the RAN that is portable across at least one hardware platform of the one or more RAN hardware platforms in the RAN hardware.
    Type: Application
    Filed: May 16, 2021
    Publication date: February 23, 2023
    Inventors: Parag Naik, Saha Anindya, Makarand Kulkami, Hernant Mallapur, Susmit Kumar Datta, Sandeep Pendharkar, Venugopal Kolathur, Sudarshan V
  • Patent number: 11544042
    Abstract: A system for deploying a Radio Access Network Containerized Network Function (RAN CNF) that is portable across a plurality of RAN hardware platforms is provided. The system includes a Software Development Kit (SDK), a schedule generator and a scheduler runtime unit. The SDK enables providing a RAN functionality in a physical layer (L1) software code in a platform-independent manner as a RAN pipeline of a plurality of RAN tasks. The RAN tasks include a first and second RAN task. The first RAN task invokes an Application programming interface (API) from a plurality of Application Programming Interfaces to call to the second RAN task. The schedule generator generates a schedule for allocating a node in the RAN pipeline to one or more processing elements. The scheduler runtime unit loads the RAN tasks corresponding to nodes in the RAN pipeline, based on the schedule generated by the schedule generator.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 3, 2023
    Assignee: SAANKHYA LABS PVT. LTD.
    Inventors: Parag Naik, Anindya Saha, Sandeep Pendharkar, Venugopal Kolathur
  • Publication number: 20220291961
    Abstract: Configurations of a system and a method for optimizing an allocation of computing resources via a disaggregated architecture, are described. In one aspect, the disaggregated architecture may include a Layer 2 (L2) controller that may be configured to optimize an allocation of computing resources in a virtualized radio access network (vRAN). The disaggregated architecture in a distributed unit may disaggregate an execution of the operations of the distributed unit by the computing resources deployed therein. Further, the disaggregated architecture may provision statistical multiplexing and provision a mechanism for allocating the computing resources based on real-time conditions in the network. The disaggregated architecture may provision a mechanism that may enable dynamic swapping, allocation, scaling up, management, and maintenance of the computing resources deployed in the distributed unit (DU).
    Type: Application
    Filed: March 14, 2022
    Publication date: September 15, 2022
    Inventors: Anindya Saha, Parag Balwant Naik, Sandeep Pendharkar, Venugopal Kolathur, Vasanth Shreesha
  • Publication number: 20220095155
    Abstract: A system and method for switching one or more User Equipment (UEs) 116A-N from a unicast mode to a broadcast or multicast mode to transmit a streaming media content to the UEs 116A-N is provided. The system includes, an Over-the-top (OTT) platform 104, a CDN 112, the UEs 116A-N, a cellular core network 202, one-to-many offload core 204, an analytics engine 206, a database 208, one-to-many transmitter 210, a real time switching module 212, a Cellular base station 214 and a user specified rules module 222. The analytics engine 206 continuously analyzes real-time and historical data stored in the database 208 to identify the UEs 116A-N that receive a streaming media content through the unicast mode and the streaming media content to be offloaded. An offload is a process by which certain portions of the streaming media content is shifted from the unicast mode to the broadcast or multicast mode.
    Type: Application
    Filed: June 5, 2020
    Publication date: March 24, 2022
    Inventors: Parag Naik, Anindya Saha, Arindam Chakraborty, Preetham Uthaiah, Sandeep Pendharkar, Yogesh Singh, Deepak Samaga
  • Patent number: 11169783
    Abstract: A method for operating a hardware-software interface (HSI) executable specification unit by means of an executable hardware-software interface (HSI) specification for a computing device is provided. The executable HSI specification is a form of a Device Programming Specification (DPS). The HSI executable specification unit includes a HSI analyser, at least one skeletal driver and a HSI executable specification interpreter.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 9, 2021
    Assignee: VAYAVYA LABS PRIVATE LIMITED
    Inventors: Sandeep Pendharkar, Parag Naik, Venugopal Kolathur, Karthick Gururaj
  • Patent number: 10949183
    Abstract: A processor-implemented method for transforming co-routines to equivalent sub-routines is provided. An input is received at a first user device from a user for a first language and a first operating environment. The first language includes the co-routines and is supported in a first hardware environment. The first language is analyzed to transform the co-routines of the first language into the sub-routines of a second language for implementing the co-routines of the first language in a second hardware environment.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 16, 2021
    Assignee: VAYAVYA LABS PRIVATE LIMITED
    Inventors: Karthick Gururaj, Sandeep Pendharkar, Venugopal Kolathur, Sangamesh O Shetty
  • Publication number: 20200249913
    Abstract: A method for operating a hardware-software interface (HSI) executable specification unit by means of an executable hardware-software interface (HSI) specification for a computing device is provided. The executable HSI specification is a form of a Device Programming Specification (DPS). The HSI executable specification unit includes a HSI analyser, at least one skeletal driver and a HSI executable specification interpreter.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 6, 2020
    Inventors: Sandeep Pendharkar, Parag Naik, Venugopal Kolathur, Karthick Gururaj
  • Publication number: 20200183671
    Abstract: A processor-implemented method for transforming co-routines to equivalent sub-routines is provided. The method includes (i) receiving, an input from user for first language and first operating environment, and (ii) analyzing first language to transform co-routines of first language into sub-routines of second language by (a) determining at least one automatic variable for persistent variables and non-persistent variables across suspend cycles or resume cycles of co-routines, (b) transforming persistent variables and non-persistent variables into sub-routines of second language based on determined automatic variables, (c) determining return statements and yield statements in co-routines of first language for transforming the return statements and yield statements into sub-routines of the second language, and (d) translating the co-routines of first language into sub-routines of second language and second operating environment.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 11, 2020
    Inventors: Karthick Gururaj, Sandeep Pendharkar, Venugopal Kolathur, Sangamesh O Shetty
  • Patent number: 10394756
    Abstract: A system and a processor implemented method for customizing an archive of a device driver generator tool for a user is provided. The system includes (i) a memory unit that stores a database, and a set of modules, and (ii) a processor. The template file obtaining module is configured to obtain information associated with the template files and template files. The configuration file obtaining module is configured to obtain information associated with the configuration files and configuration files. The archive configuration file verification module is configured to verify whether an archive for the configuration files and the template files is pre-existing in the database. The archive file appending module is configured to (i) append the template files and the configuration files to the archive pre-existing in the database. The archive file appending module generates the archive for template files and configuration files upon the archive not pre-existing in the database.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 27, 2019
    Inventors: Uma Bondada, Sandeep Pendharkar, Venugopal Kolathur
  • Patent number: 10007492
    Abstract: A system and method for automatically generating device driver codes for a device model based on an operation of said device model in verification environments is provided. The System includes a computing device. The computing device includes a device programming specification receiving module, a run time specification parsing module, a verification environment determination module and a driver generation module. The device programming specification receiving module receives at least one device programming specification aspects associated with an operation of device model in verification environment to determine a type of device driver code to be generated. The run time specification parsing module parses a run time specification file that includes verification environment parameters in run time specification. The verification environment determination module determines whether the verification environment equals to a part of a simulation/emulation in run time specification.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 26, 2018
    Inventors: Sandeep Pendharkar, Venugopal Kolathur, Karthick Gururaj
  • Publication number: 20170115969
    Abstract: A system and method for automatically generating device driver codes for a device model based on an operation of said device model in verification environments is provided. The System includes a computing device. The computing device includes a device programming specification receiving module, a run time specification parsing module, a verification environment determination module and a driver generation module. The device programming specification receiving module receives at least one device programming specification aspects associated with an operation of device model in verification environment to determine a type of device driver code to be generated. The run time specification parsing module parses a run time specification file that includes verification environment parameters in run time specification. The verification environment determination module determines whether the verification environment equals to a part of a simulation/emulation in run time specification.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 27, 2017
    Inventors: Sandeep Pendharkar, Venugopal Kolathur, Karthick Gururaj
  • Patent number: 9460261
    Abstract: A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 4, 2016
    Inventors: Srivatsan Raghavan, Karthick Gururaj, Sandeep Pendharkar, Someshwar DK, Shrinivas Nagaraddi
  • Patent number: 9372770
    Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyzes the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: June 21, 2016
    Inventors: Karthick Gururaj, Sandeep Pendharkar, Parag Naik, Ragesh Thottathil Ramachandran, Deepanjan Kar
  • Patent number: 9250868
    Abstract: A system for generating a device driver based on an archived template code using a device driver generation tool is provided. The device driver generation tool is configured to extract configuration files and template files from a template archive stored in a database, each of the files comprises high level configuration files and low level configuration files, each comprising one or more labels, parse a high-level configuration file, corresponding to a class of a device, and an operating system for which the driver is being generated, process a label from the high-level configuration file, extract template code from the template files to obtain an extracted template code, and generate a portion of the driver based on the extracted template code when a block label is identified, parse a low-level configuration file, and generate the driver using a first specification and a second specification when the label is a file label.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 2, 2016
    Inventors: Uma Bondada, Sandeep Pendharkar, Venugopal Kolathur
  • Publication number: 20150310159
    Abstract: A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences.
    Type: Application
    Filed: March 4, 2015
    Publication date: October 29, 2015
    Inventors: Srivatsan Raghavan, Karthick Gururaj, Sandeep Pendharkar, Someshwar DK, Shrinivas Nagaraddi
  • Publication number: 20150278231
    Abstract: A system and a processor implemented method for customizing an archive of a device driver generator tool for a user is provided. The system includes (i) a memory unit that stores a database, and a set of modules, and (ii) a processor. The template file obtaining module is configured to obtain information associated with the template files and template files. The configuration file obtaining module is configured to obtain information associated with the configuration files and configuration files. The archive configuration file verification module is configured to verify whether an archive for the configuration files and the template files is pre-existing in the database. The archive file appending module is configured to (i) append the template files and the configuration files to the archive pre-existing in the database. The archive file appending module generates the archive for template files and configuration files upon the archive not pre-existing in the database.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 1, 2015
    Inventors: Uma Bondada, Sandeep Pendharkar, Venugopal Kolathur
  • Publication number: 20150089515
    Abstract: A system for generating a device driver based on an archived template code using a device driver generation tool is provided. The device driver generation tool is configured to extract configuration files and template files from a template archive stored in a database, each of the files comprises high level configuration files and low level configuration files, each comprising one or more labels, parse a high-level configuration file, corresponding to a class of a device, and an operating system for which the driver is being generated, process a label from the high-level configuration file, extract template code from the template files to obtain an extracted template code, and generate a portion of the driver based on the extracted template code when a block label is identified, parse a low-level configuration file, and generate the driver using a first specification and a second specification when the label is a file label.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 26, 2015
    Inventors: Uma Bondada, Sandeep Pendharkar, Venugopal Kolathur
  • Publication number: 20130326275
    Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyses the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 5, 2013
    Inventors: Karthick Gururaj, Sandeep Pendharkar, Parag Naik, Ragesh Thottathil Ramachandran, Deepanjan Kar
  • Patent number: 6024885
    Abstract: A process of patterning magnetic multilayer films including the steps of successively depositing a plurality of magnetic multilayer films on a supporting substrate, selectively removing portions of the plurality of magnetic multilayer films using a reactive plasma etch including chlorine gas, and passivating in situ, or an adjacent evacuated chamber, remaining portions of the plurality of magnetic multilayer films, i.e. the memory elements, in a post-etch fluorinated plasma.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: February 15, 2000
    Assignee: Motorola, Inc.
    Inventors: Sandeep Pendharkar, Douglas J. Resnick