Patents by Inventor Sandeep Razdan
Sandeep Razdan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210055489Abstract: An optical connection assembly joining optical components is described. The optical connection assembly is manufactured using a fan out wafer level packaging to produce dies/frames which include mechanical connection features. A fastener is joined to a connection component and affixed to the mechanical connection features, to provide structural support to the connection between the connected component and the die/frame structure.Type: ApplicationFiled: August 19, 2019Publication date: February 25, 2021Inventors: Ashley J. MAKER, Joyce J. M. PETERNEL, Sandeep RAZDAN, Matthew J. TRAVERSO, Aparna R. PRASAD
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Patent number: 10877219Abstract: The present disclosure provides for periscope optical assemblies within interposers that include a bulk material having a first side and a second side opposite to the first side; a first optic defined in the bulk material at a first height in the bulk material along an axis extending between the first second sides; a second optic defined in the bulk material at a second height in the bulk material, different than the first height, along the axis; a first waveguide defined in the bulk material, extending from the first side to the first optic; a second waveguide defined in the bulk material, extending from the second optic to the second side; and a third waveguide defined in the bulk material, extending from the first optic to the second optic.Type: GrantFiled: August 20, 2019Date of Patent: December 29, 2020Assignee: Cisco Technology, Inc.Inventors: Matthew J. Traverso, Ashley J. Maker, Sandeep Razdan
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Publication number: 20200319416Abstract: The present disclosure provides a frame lid assembly, which may be used in assembling an optical platform to provide isolated thermal conduction paths for various elements thereof. The frame lid assembly includes a first frame lid, including: a foot, disposed in a first plane; a roof, disposed in a second plane parallel to the first plane, the roof defining a port as a first through-hole that is perpendicular to the second plane; a wall, disposed obliquely to the first plane, separating the roof from the foot, the wall defining a slot as a second through-hole that is parallel to the first plane; a second frame lid connected to the first frame lid and thermally isolated from the first frame lid, the second frame lid including: a cap, connected to the roof via a thermal insulator; and a plug, extending perpendicularly from the cap through the port.Type: ApplicationFiled: July 25, 2019Publication date: October 8, 2020Inventors: Vipulkumar K. PATEL, Aparna R. PRASAD, Sandeep RAZDAN
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Publication number: 20200241207Abstract: Using laser patterning for an optical assembly, optical features are written into photonic elements at the end of a manufacturing sequence in order to prevent errors and damages to the optical features. The optical assembly is manufactured by affixing a photonic element to a substrate which includes one or more optical features and mapping one or more optical features for the photonic element. The optical features are then written into the fixed photonic element using laser patterning and the optical assembly is completed by connecting components, such as optical fibers, to the photonic element.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Inventors: Sandeep RAZDAN, Ashley J. MAKER, Jock T. BOVINGTON, Matthew J. TRAVERSO
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Patent number: 10727368Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.Type: GrantFiled: April 1, 2016Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Myung Jin Yim, Seungjae Lee, Sandeep Razdan
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Patent number: 10564352Abstract: Aspects described herein include a method comprising forming an insulator layer above a silicon layer of a silicon-on-insulator (SOI) substrate. A first optical device is formed partly in the silicon layer and partly in the insulator layer. A first optical waveguide is formed in the insulator layer and optically coupled with the first optical device. The method further comprises forming conductive contacts extending partly through the insulator layer to the first optical device, bonding a first surface of an interposer with a top surface of the insulator layer, and forming, from a second surface of the interposer opposite the first surface, a plurality of first conductive vias extending at least partly through the interposer. The plurality of first conductive vias are coupled with the conductive contacts.Type: GrantFiled: August 16, 2019Date of Patent: February 18, 2020Assignee: Cisco Technology, Inc.Inventors: Sandeep Razdan, Ashley J. Maker, Matthew J. Traverso, Mark A. Webster, Jock T. Bovington
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Publication number: 20190326266Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.Type: ApplicationFiled: April 24, 2018Publication date: October 24, 2019Inventors: Matthew J. TRAVERSO, Sandeep RAZDAN, Ashley J. MAKER
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Patent number: 10393959Abstract: A method comprises bonding a first surface of an interposer wafer with a first exterior surface of a photonic wafer assembly. The photonic wafer assembly comprises one or more optical devices coupled with one or more metal layers and with one or more first optical waveguides. The method further comprises forming, from a second surface opposite the first surface, a plurality of first conductive vias extending at least partway through the interposer wafer and coupled with the one or more metal layers. The method further comprises forming, at the second surface, a plurality of first conductive pads coupled with the plurality of first conductive vias. The method further comprises forming one or more second conductive pads coupled with the one or more metal layers. The one or more second conductive pads are accessible at a second exterior surface of the photonic wafer assembly opposite the first exterior surface.Type: GrantFiled: October 26, 2018Date of Patent: August 27, 2019Assignee: Cisco Technology, Inc.Inventors: Sandeep Razdan, Ashley J. Maker, Matthew J. Traverso, Mark A. Webster, Jock T. Bovington
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Publication number: 20190006549Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.Type: ApplicationFiled: April 1, 2016Publication date: January 3, 2019Inventors: Myung Jin YIM, Seungjae LEE, Sandeep RAZDAN
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Patent number: 10145758Abstract: Embodiments herein describe techniques for testing optical components in a photonic chip using a testing structure disposed in a sacrificial region of a wafer. In one embodiment, the wafer is processed to form multiple photonic chips integrated into the wafer. While forming optical components in the photonic chips (e.g., modulators, detectors, waveguides, etc.), a testing structure can be formed in one or more sacrificial regions in the wafer. In one embodiment, the testing structure is arranged near an edge coupler in the photonic chip such that an optical signal can be transferred between the photonic chip and the testing structure. Moreover, the testing structure has a grating coupler disposed at or near a top surface of the wafer which permits optical signals to be transmitted into, or received from, the grating coupler when an optical probe is arranged above the grating coupler.Type: GrantFiled: April 28, 2017Date of Patent: December 4, 2018Assignee: Cisco Technology, Inc.Inventors: Matthew J. Traverso, Ravi S. Tummidi, Mark A. Webster, Sandeep Razdan
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Patent number: 10128225Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.Type: GrantFiled: February 17, 2017Date of Patent: November 13, 2018Assignee: INTEL CORPORATIONInventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
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Publication number: 20180313718Abstract: Embodiments herein describe techniques for testing optical components in a photonic chip using a testing structure disposed in a sacrificial region of a wafer. In one embodiment, the wafer is processed to form multiple photonic chips integrated into the wafer. While forming optical components in the photonic chips (e.g., modulators, detectors, waveguides, etc.), a testing structure can be formed in one or more sacrificial regions in the wafer. In one embodiment, the testing structure is arranged near an edge coupler in the photonic chip such that an optical signal can be transferred between the photonic chip and the testing structure. Moreover, the testing structure has a grating coupler disposed at or near a top surface of the wafer which permits optical signals to be transmitted into, or received from, the grating coupler when an optical probe is arranged above the grating coupler.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Applicants: Cisco Technology, Inc., Cisco Technology, Inc.Inventors: Matthew J. TRAVERSO, Ravi S. TUMMIDI, Mark A. WEBSTER, Sandeep RAZDAN
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Patent number: 9964719Abstract: The present disclosure discloses an assembly. The assembly includes a photonic chip and an electrical chip disposed side by side. The assembly also includes mold compound that encapsulates the photonic chip and the electrical chip. The assembly further includes a redistribution layer (RDL) that extends across the top surface of the photonic chip and the top surface of the electrical chip and connects the photonic chip with the electrical chip. Moreover, the photonic chip includes an exposed optical interface for transmitting optical signals between the photonic chip and an external optical device.Type: GrantFiled: April 28, 2017Date of Patent: May 8, 2018Assignee: Cisco Technology, Inc.Inventors: Sandeep Razdan, Vipulkumar Patel, Matthew J. Traverso
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Patent number: 9791640Abstract: An interposer for coupling an optical conduit to an optical component, said interposer comprising: (a) an optical component; (b) a first lens component having a first lens; (c) a second lens component having a second lens, said first and second lenses being configured to define an expanded-beam coupling therebetween; (d) at least one reflective surface optically coupled with said second lens; (e) a first optical path at least partially defined between said optical component and said first lens to accommodate a diverging light beam from said optical component to said first lens; (f) a second optical path at least partially defined between said second lens and said at least one reflective surface to accommodate a converging light beam from said second lens and said at least one reflective surface; and (g) a separable interface along said second optical path or at said expanded-beam coupling.Type: GrantFiled: March 14, 2016Date of Patent: October 17, 2017Assignee: TE Connectivity CorporationInventors: Terry Patrick Bowen, William A. Weeks, James Toth, Jibin Sun, Sandeep Razdan
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Publication number: 20170288780Abstract: Apparatuses including integrated circuit (IC) optical assemblies and processes for fabrication of IC optical assemblies are disclosed herein. In some embodiments, the IC optical assemblies include an optical transmitter component electrically coupled to a first portion of a packaging substrate. The IC optical assemblies further include an optical transmitter driver component between the optical transmitter component and a second portion of the packaging substrate, wherein a first side of the optical transmitter driver component is electrically coupled to the optical transmitter component. The IC optical assemblies further include a plurality of bumps between a second side of the optical transmitter driver component and proximate the second portion of the packaging substrate, wherein the plurality of bumps are not directly coupled to the optical transmitter driver component.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Myung Jin Yim, Quan A. Tran, SeungJae Lee, Sandeep Razdan, Yigit O. Yilmaz, Pradeep Srinivasan, Jincheng Wang, Ansheng Liu
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Publication number: 20170261703Abstract: An interposer for coupling an optical conduit to an optical component, said interposer comprising: (a) an optical component; (b) a first lens component having a first lens; (c) a second lens component having a second lens, said first and second lenses being configured to define an expanded-beam coupling therebetween; (d) at least one reflective surface optically coupled with said second lens; (e) a first optical path at least partially defined between said optical component and said first lens to accommodate a diverging light beam from said optical component to said first lens; (f) a second optical path at least partially defined between said second lens and said at least one reflective surface to accommodate a converging light beam from said second lens and said at least one reflective surface; and (g) a separable interface along said second optical path or at said expanded-beam coupling.Type: ApplicationFiled: March 14, 2016Publication date: September 14, 2017Inventors: Terry Patrick Bowen, William A. Weeks, James Toth, Jibin Sun, Sandeep Razdan
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Publication number: 20170229438Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 17, 2017Publication date: August 10, 2017Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
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Publication number: 20170195043Abstract: An electrochromic test port provides an actively tunable system for building an optical test port for an optical waveguide with enhanced SNR properties over conventional approaches.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventors: HAIPENG ZHANG, SANDEEP RAZDAN, JIBIN SUN, NICOLA PUGLIANO
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Patent number: 9613934Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.Type: GrantFiled: February 13, 2015Date of Patent: April 4, 2017Assignee: INTEL CORPORATIONInventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
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Publication number: 20170042043Abstract: A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250° C.-300° C. at a ramp rate of 50° C./second-100° C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Inventors: SIVAKUMAR NAGARAJAN, SANDEEP RAZDAN, NISHA ANANTHAKRISHNAN, CRAIG J. WEINMAN, KABIRKUMAR J. MIRPURI