Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250° C.-300° C. at a ramp rate of 50° C./second-100° C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: One aspect of the invention provides an optoelectronics structure including: a substrate defining a trench on a first surface; and a VCSEL structure mounted vertically within the trench of the substrate such that the VCSEL structure emits a laser beam substantially parallel to the substrate. Another aspect of the invention provides an optoelectronics structure including: an fiber guiding substrate defining a trench on a first surface; a VCSEL structure mounted vertically within the trench of the fiber guiding substrate such that the VCSEL structure emits a laser beam substantially parallel to the substrate; and an optical fiber mounted on the fiber guiding substrate substantially coaxial with the laser beam emitted by the VCSEL structure.

Abstract: One aspect of the invention provides a method of fabricating a mode size converter. The method includes: exposing a photoresist-coated substrate to varying doses of light exposure to produce a profile in the photoresist of a beam mode size converter; and etching the photoresist-coated substrate to remove an equal thickness of the photoresist and substrate. The beam mode sized converter includes: a first surface having a first surface height and a first surface width; a second surface opposite the first surface, the second surface having a second surface height different than the first surface height and a second surface width different than the first surface width; and one or more boundary surfaces connecting the first surface and second surfaces.

Abstract: One aspect of the invention provides a mode size converter having a first end and a second end. The mode size converter includes: a silicon waveguide having an inverse taper from the first end; and a silicon nitride waveguide having an inverse taper relative to the first end. The silicon nitride waveguide is adjacent and substantially parallel to the silicon waveguide. Another aspect of the invention provides an optical assembly including: a mode size converter as described herein; and a fiber optic optically coupled to the silicon nitride waveguide at the second end of the mode size converter.

Abstract: One aspect of the invention provides a method of fabricating a mode size converter. The method includes: exposing a photoresist-coated substrate to varying doses of light exposure to produce a profile in the photoresist of a beam mode size converter; and etching the photoresist-coated substrate to remove an equal thickness of the photoresist and substrate. The beam mode sized converter includes: a first surface having a first surface height and a first surface width; a second surface opposite the first surface, the second surface having a second surface height different than the first surface height and a second surface width different than the first surface width; and one or more boundary surfaces connecting the first surface and second surfaces.

Abstract: One aspect of the invention provides an optoelectronics structure including: a substrate defining a trench on a first surface; and a VCSEL structure mounted vertically within the trench of the substrate such that the VCSEL structure emits a laser beam substantially parallel to the substrate. Another aspect of the invention provides an optoelectronics structure including: an fiber guiding substrate defining a trench on a first surface; a VCSEL structure mounted vertically within the trench of the fiber guiding substrate such that the VCSEL structure emits a laser beam substantially parallel to the substrate; and an optical fiber mounted on the fiber guiding substrate substantially coaxial with the laser beam emitted by the VCSEL structure.

Abstract: An optical assembly comprising: (a) a substrate having a first planar surface; (b) an optical component connected to the substrate and having a second planar surface parallel to the first surface and at least one first optical axis; (c) a plurality of optical fiber stubs having a certain diameter and being disposed at least partially between the substrate and the optical component; (d) at least one of the substrate or the optical component having one or more grooves on the first or second surfaces, respectively, such that each groove is configured to receive one of the plurality of fiber stubs such that each of the fiber stubs protrudes a first distance from the first or second surface to space the first surface the first distance from the second surface; and (e) a least one optical conduit having a second optical axis, the optical conduit being disposed on the first or second surface such that the second optical axis is optically aligned with the first optical axis.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

Abstract: A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250° C.-300° C. at a ramp rate of 50° C./second-100° C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5.

Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.

Abstract: Nanocomposite compositions containing a graft polymer and a filler such as nano-sized silica having flame resistant properties are described.

Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.

Abstract: Methods for coating a protective material on a semiconductor substrate to protect a back surface thereof from defects are provided, by depositing a diamond-like coating (DLC) material thereon at a low temperature, e.g. between about 150° C. to about 350° C.