Patents by Inventor Sandhya Dwarkadas
Sandhya Dwarkadas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9411733Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.Type: GrantFiled: September 7, 2012Date of Patent: August 9, 2016Assignee: University of RochesterInventors: Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas
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Patent number: 8661204Abstract: The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.Type: GrantFiled: March 16, 2012Date of Patent: February 25, 2014Assignee: University of Rochester, Office of Technology TransferInventors: Sandhya Dwarkadas, Arrvindh Shriraman, Michael Scott
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Publication number: 20140032848Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.Type: ApplicationFiled: September 7, 2012Publication date: January 30, 2014Applicant: UNIVERSITY OF ROCHESTERInventors: Hongzhou ZHAO, Arrvindh SHRIRAMAN, Sandhya DWARKADAS
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Publication number: 20120179877Abstract: The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.Type: ApplicationFiled: March 16, 2012Publication date: July 12, 2012Applicant: University of Rochester, Office of Technology TransferInventors: Arrvindh SHRIRAMAN, Sandhya DWARKADAS, Michael SCOTT
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Patent number: 8180971Abstract: In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.Type: GrantFiled: October 26, 2010Date of Patent: May 15, 2012Assignee: University of RochesterInventors: Michael Scott, Sandhya Dwarkadas, Arrvindh Shriraman, Virendra Marathe, Michael F. Spear
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Patent number: 8103856Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.Type: GrantFiled: January 12, 2009Date of Patent: January 24, 2012Assignee: University of RochesterInventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
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Publication number: 20110099335Abstract: In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.Type: ApplicationFiled: October 26, 2010Publication date: April 28, 2011Applicant: University of RochesterInventors: Michael L. Scott, Sandhya Dwarkadas, Arrvindh Shriraman, Virendra Marathe, Michael F. Spear
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Patent number: 7739537Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.Type: GrantFiled: March 27, 2006Date of Patent: June 15, 2010Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael L. Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
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Publication number: 20090216997Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.Type: ApplicationFiled: January 12, 2009Publication date: August 27, 2009Inventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
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Patent number: 7490220Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.Type: GrantFiled: June 8, 2005Date of Patent: February 10, 2009Inventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
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Publication number: 20080059968Abstract: Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method comprises the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.Type: ApplicationFiled: October 29, 2007Publication date: March 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Cascaval, Evelyn Duesterwald, Sandhya Dwarkadas
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Patent number: 7289939Abstract: Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method comprises the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.Type: GrantFiled: May 4, 2006Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Gheorghe C. Cascaval, Evelyn Duesterwald, Sandhya Dwarkadas
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Publication number: 20070016817Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.Type: ApplicationFiled: March 27, 2006Publication date: January 18, 2007Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
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Publication number: 20060217940Abstract: Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method comprises the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.Type: ApplicationFiled: May 4, 2006Publication date: September 28, 2006Applicant: International Business Machines CorporationInventors: Gheorghe Cascaval, Evelyn Duesterwald, Sandhya Dwarkadas
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Patent number: 7089443Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.Type: GrantFiled: January 23, 2004Date of Patent: August 8, 2006Assignee: University of RochesterInventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael L. Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
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Patent number: 7072805Abstract: Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method includes the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.Type: GrantFiled: October 17, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Gheorghe C. Cascaval, Evelyn Duesterwald, Sandhya Dwarkadas
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Publication number: 20060106923Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.Type: ApplicationFiled: June 8, 2005Publication date: May 18, 2006Inventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
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Publication number: 20050086029Abstract: Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method comprises the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Cascaval, Evelyn Duesterwald, Sandhya Dwarkadas
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Patent number: RE41958Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.Type: GrantFiled: December 21, 2006Date of Patent: November 23, 2010Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosunoglu, David H. Albonesi
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Patent number: RE42213Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.Type: GrantFiled: January 24, 2006Date of Patent: March 8, 2011Assignee: University of RochesterInventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosunoglu, David H. Albonesi