Patents by Inventor Sandhya Dwarkadas

Sandhya Dwarkadas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050060597
    Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.
    Type: Application
    Filed: January 23, 2004
    Publication date: March 17, 2005
    Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
  • Patent number: 6834328
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: December 21, 2004
    Assignee: University of Rochester
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu, David Albonesi
  • Publication number: 20040184340
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Application
    Filed: January 27, 2004
    Publication date: September 23, 2004
    Applicant: UNIVERSITY OF ROCHESTER
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu, David Albonesi
  • Patent number: 6684298
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: January 27, 2004
    Assignee: University of Rochester
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu, David Albonesi
  • Patent number: 6341339
    Abstract: The present invention discloses an apparatus and method for maintaining the coherence of data within a shared memory network including a plurality of nodes. The system utilizes processors monitoring the occurrence of particular processing events within a local memory storage area. Upon the detection of events indicating the change of status of a particular group of data, a comparison is made between a modified copy of the group of data and a clean copy of the group of data to detect any modifications made to the group of data. These modifications are entered into the clean copy of the group of data and processing continues.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: January 22, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Leonidas Kontothanassis, Michael L. Scott, Robert Stets, Sandhya Dwarkadas, Nikos Hardavellas, Galen Hunt