Patents by Inventor Sandip Halder

Sandip Halder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076865
    Abstract: A federated machine learning method is provided. The method includes providing, from a central model server, an initial trained machine learning (ML) model to a plurality of clients as a respective local ML model. The initial trained ML model is configured to identify defect features from scanning electron microscopy (SEM) images. The method additionally includes receiving, from at least one client by the central model server, information indicative of a respective updated local ML model. The method also includes determining, based on the information indicative of the respective updated local ML models, an updated global ML model.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Inventors: Bappaditya Dey, Enrique Dehaerne, Sandip Halder
  • Publication number: 20250076866
    Abstract: A method for training a local machine learning model is provided. The method includes receiving a scanning electron microscope (SEM) image of semiconductor features. The method additionally includes determining a location and dimensions of a bounding box within the SEM image. The method yet further includes determining, whether a defect feature exists within the bounding box, based on an unsupervised object detection process. The method also includes, if the defect feature exists within the bounding box, receiving positive rewards. The method also includes, if the defect feature does not exist within the bounding box, receiving negative rewards.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Inventors: Bappaditya Dey, Enrique Dehaerne, Sandip Halder
  • Patent number: 12243193
    Abstract: The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 4, 2025
    Assignee: IMEC VZW
    Inventors: Bappaditya Dey, Sandip Halder, Gouri Sankar Kar, Victor M. Blanco, Senthil Srinivasan Shanmugam Vadakupudhu Palayam
  • Patent number: 12066763
    Abstract: A characterization system for inspecting or performing metrology on a layer within a semiconductor stack is disclosed. The system includes an imaging sub-system configured to acquire image data from a semiconductor stack including one or more layers. The semiconductor stack includes a metal layer having a thickness between 0.5 and 10 nm deposited on a layer of the semiconductor stack to form a reflective surface on the layer. The system includes a controller. The controller is configured to receive image data of the reflective surface on the layer of the substrate stack and identify one or more defects or one or more structures within the layer based on illumination reflected from the reflective surface.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 20, 2024
    Assignee: KLA Corporation
    Inventors: Kaushik Sah, Andrew James Cross, Sandip Halder, Sayantan Das
  • Publication number: 20230343078
    Abstract: The present disclosure related to a computer-implemented training and prediction method for defect detection, classification and segmentation in image data. The training method comprises providing an ensemble of learning structures, each learning structure comprising a feature extractor module, a region proposal module, a detection module, and a segmentation module. Each learning structure is trained individually and validated. Learning structures whose validation prediction score exceeds a predetermined threshold score are selected and their predictions combined, using a parametrized ensemble voting structure.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 26, 2023
    Inventors: Bappaditya Dey, Enrique Dehaerne, Sandip Halder
  • Publication number: 20230342965
    Abstract: This application discloses a computing system to obtain a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design. The computing system can implement an unsupervised deep learning algorithm to process the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image. The computing system can extract contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device without use of the layout design or a mask design. The computing system can calibrate the layout design or the mask design describing the one or more lithographic masks based, at least in part, on the contours extracted from the denoised wafer image.
    Type: Application
    Filed: August 31, 2022
    Publication date: October 26, 2023
    Inventors: Germain Louis Fenger, Mark Pereira, Bhamidipati Venkata Rama Samir, Sandip Halder, Bappaditya Dey, Hsin-Wei Wu, Kiarash Ahi
  • Publication number: 20220244648
    Abstract: A characterization system for inspecting or performing metrology on a layer within a semiconductor stack is disclosed. The system includes an imaging sub-system configured to acquire image data from a semiconductor stack including one or more layers. The semiconductor stack includes a metal layer having a thickness between 0.5 and 10 nm deposited on a layer of the semiconductor stack to form a reflective surface on the layer. The system includes a controller. The controller is configured to receive image data of the reflective surface on the layer of the substrate stack and identify one or more defects or one or more structures within the layer based on illumination reflected from the reflective surface.
    Type: Application
    Filed: February 4, 2021
    Publication date: August 4, 2022
    Inventors: Kaushik Sah, Andrew James Cross, Sandip Halder, Sayantan Das
  • Publication number: 20220076383
    Abstract: The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.
    Type: Application
    Filed: July 2, 2021
    Publication date: March 10, 2022
    Inventors: Bappaditya Dey, Sandip Halder, Gouri Sankar Kar, Victor M. Blanco, Senthil Srinivasan Shanmugam Vadakupudhu Palayam
  • Patent number: 10818504
    Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 27, 2020
    Assignee: IMEC VZW
    Inventors: Waikin Li, Danilo De Simone, Sandip Halder, Frederic Lazzarino
  • Patent number: 10732124
    Abstract: Example embodiments relate to methods for detecting defects of a lithographic pattern. One example embodiment includes a method for detecting defects of a lithographic pattern on a semiconductor wafer that includes a plurality of die areas. Each of the die areas has a region of interest (ROI) that includes a plurality of features forming the lithographic pattern. The method includes acquiring an image of at least one of the ROIs. The method also includes removing features touching an edge of the image. Further, the method includes counting a number of remaining features in the image.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 4, 2020
    Assignee: IMEC VZW
    Inventors: Sandip Halder, Philippe Leray
  • Publication number: 20190189458
    Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 20, 2019
    Applicant: IMEC VZW
    Inventors: Waikin Li, Danilo De Simone, Sandip Halder, Frederic Lazzarino
  • Publication number: 20190079023
    Abstract: Example embodiments relate to methods for detecting defects of a lithographic pattern. One example embodiment includes a method for detecting defects of a lithographic pattern on a semiconductor wafer that includes a plurality of die areas. Each of the die areas has a region of interest (ROI) that includes a plurality of features forming the lithographic pattern. The method includes acquiring an image of at least one of the ROIs. The method also includes removing features touching an edge of the image. Further, the method includes counting a number of remaining features in the image.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Applicant: IMEC VZW
    Inventors: Sandip Halder, Philippe Leray
  • Patent number: 10061209
    Abstract: The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 28, 2018
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Julien Mailfert, Philippe Leray, Sandip Halder
  • Patent number: 9983154
    Abstract: The present disclosure is related to a method for detection of defects in a printed pattern of geometrical features on a semiconductor die, the pattern comprising an array of features having a nominal pitch, the method comprising determining deviations from the nominal pitch in the printed pattern, and comparing the printed pattern with another version of the pattern, the other version having the same or similar pitch deviations as the printed pattern. According to various embodiments, the other version of the pattern may a printed pattern on a second die, or it may be a reference pattern, obtained by shifting features of the array in a version having no or minimal pitch deviations, so that the pitch deviations in the reference pattern are the same or similar to the pitch deviations in the printed pattern under inspection.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: May 29, 2018
    Assignee: IMEC VZW
    Inventors: Sandip Halder, Philippe Leray
  • Patent number: 9874821
    Abstract: The present disclosure is related to a method for detecting and ranking hotspots in a lithographic mask used for printing a pattern on a substrate. According to example embodiments, the ranking is based on defect detection on a modulated focus wafer or a modulated dose wafer, where the actual de-focus or dose value at defect locations is taken into account, in addition to a de-focus or dose setting applied to a lithographic tool when a mask pattern is printed on the wafer. Additionally or alternatively, lithographic parameters other than the de-focus or dose can be used as a basis for the ranking method.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 23, 2018
    Assignee: IMEC VZW
    Inventors: Sandip Halder, Dieter Van Den Heuvel, Vincent Truffert, Philippe Leray
  • Publication number: 20170167992
    Abstract: The present disclosure is related to a method for detection of defects in a printed pattern of geometrical features on a semiconductor die, the pattern comprising an array of features having a nominal pitch, the method comprising determining deviations from the nominal pitch in the printed pattern, and comparing the printed pattern with another version of the pattern, the other version having the same or similar pitch deviations as the printed pattern. According to various embodiments, the other version of the pattern may a printed pattern on a second die, or it may be a reference pattern, obtained by shifting features of the array in a version having no or minimal pitch deviations, so that the pitch deviations in the reference pattern are the same or similar to the pitch deviations in the printed pattern under inspection.
    Type: Application
    Filed: November 11, 2016
    Publication date: June 15, 2017
    Applicant: IMEC VZW
    Inventors: Sandip Halder, Philippe Leray
  • Publication number: 20170052452
    Abstract: The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.
    Type: Application
    Filed: May 9, 2016
    Publication date: February 23, 2017
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Julien Mailfert, Philippe Leray, Sandip Halder
  • Publication number: 20160313647
    Abstract: The present disclosure is related to a method for detecting and ranking hotspots in a lithographic mask used for printing a pattern on a substrate. According to example embodiments, the ranking is based on defect detection on a modulated focus wafer or a modulated dose wafer, where the actual de-focus or dose value at defect locations is taken into account, in addition to a de-focus or dose setting applied to a lithographic tool when a mask pattern is printed on the wafer. Additionally or alternatively, lithographic parameters other than the de-focus or dose can be used as a basis for the ranking method.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 27, 2016
    Applicant: IMEC VZW
    Inventors: Sandip Halder, Dieter Van Den Heuvel, Vincent Truffert, Philippe Leray
  • Patent number: 8735182
    Abstract: A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P1 for forming the structure; measuring the mass M1 of the substrate; performing thermal treatment; measuring the mass M2 of the substrate; calculating the mass difference between the mass of the substrate measured before and after the performed thermal treatment; and deducing the presence of embedded voids in the structure by comparing the mass difference with a pre-determined value.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: May 27, 2014
    Assignee: IMEC
    Inventors: Leonardus Leunissen, Sandip Halder, Eric Beyne
  • Patent number: 8513163
    Abstract: A high-temperature superconducting thin-film strip conductor (HTSL-CC) includes a metal substrate, a buffer layer chemically generated thereon and grown crystallographically unrotated in relation to the metal substrate, and a chemically generated superconducting coating thereon. The HTSL-CC possesses high texturing of the buffer layer since the metal substrate has a surface roughness RMS<50 nm, and since and the buffer layer is grown directly onto its surface, without an intermediate layer, crystallographically unrotated in relation to the crystalline structure of the metal substrate.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: August 20, 2013
    Assignee: BASF SE
    Inventors: Michael Baecker, Theodor Schneller, Sandip Halder