Abstract: In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell. A resistance-switching material is then deposited between and above the bottom electrode structures, followed by a top electrode layer. Or, insulation is deposited between and above the bottom electrode structures, followed by planarizing and a wet etch to expose top surfaces of the bottom electrode structures, then deposition of the resistance-switching material and the top electrode layer. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.

Abstract: Provided are resistive random access memory (ReRAM) cells having bi-layered metal oxide structures. The layers of a bi-layered structure may have different compositions and thicknesses. Specifically, one layer may be thinner than the other layer, sometimes as much as 5 to 20 times thinner. The thinner layer may be less than 30 Angstroms thick or even less than 10 Angstroms thick. The thinner layer is generally more oxygen rich than the thicker layer. Oxygen deficiency of the thinner layer may be less than 5 atomic percent or even less than 2 atomic percent. In some embodiments, a highest oxidation state metal oxide may be used to form a thinner layer. The thinner layer typically directly interfaces with one of the electrodes, such as an electrode made from doped polysilicon. Combining these specifically configured layers into the bi-layered structure allows improving forming and operating characteristics of ReRAM cells.

Abstract: Provided are ReRAM cells, each having at least one interface between an electrode and a resistive switching layers with a maximum field value of less than 0.25. The electrode materials forming such interfaces include tantalum nitrides doped with lanthanum, aluminum, erbium yttrium, or terbium (e.g., TaX(Dopant)YN, where X is at least about 0.95). The electrode materials have low work functions (e.g., less than about 4.5 eV). At the same time, the resistive switching materials have high relative dielectric permittivities (e.g., greater than about 30) and high electron affinities (greater than about for 3.5 eV). Niobium oxide is one example of a suitable resistive switching material. Another electrode interfacing the resistive switching layer may have different characteristics and, in some embodiments, may be an inert electrode.

Abstract: A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer. The resistive switching layer comprises a metal oxide and is disposed between the first electrode layer and the second electrode layer. The elemental metal selected for each of the first and second electrode layers is the same metal as selected to form the metal oxide resistive switching layer. The use of common metal materials within the memory element eliminates the growth of unwanted and incompatible native oxide interfacial layers that create undesirable circuit impedance.

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract: A memory is described that includes a shared diode layer and a memory element coupled to the diode layer. The memory element has a pie slice-shape, and includes a sidewall having a carbon film thereon. Numerous other aspects are also disclosed.

Abstract: Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.

Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.

Abstract: A MIIIM diode and method of fabricating are disclosed. In one aspect, the MIIIM diode comprises a first metal electrode, a first region comprising a first insulator material having an interface with the first metal electrode, a second region comprising a second insulator material having an interface with the first insulator material, a third region comprising a third insulator material having an interface with the second insulator material, and a second metal electrode having an interface with the third insulator material. At least one of the first, second, or third insulator materials is lanthanum oxide.

Abstract: In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.

Abstract: A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.

Abstract: Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.

Abstract: A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided.