Abstract: Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.

Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Abstract: In a first aspect, a metal-insulator-metal (“MIM”) stack is provided that includes a first conductive layer, a resistivity-switching layer having a metal oxide layer formed above the first conductive layer, a material layer between the first conductive layer and the resistivity-switching layer, and a second conductive layer above the resistivity-switching layer. The first conductive layer includes a multi-layer metal-silicide stack, and the material layer has a Gibbs free energy of formation per O between about ?3 and ?6 eV. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.

Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.

Abstract: A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract: A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.