Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract: A printed circuit board (PCB) includes a plurality of layers and electronic components connected to its top surface. The PCB also includes a plurality of trace layers, each located at a respective depth within the layers of the PCB. A plurality of vias provide signal pathways for the trace layer. Upon their manufacture, the vias include a stub portion not necessary for the signal pathways and causing degradation of the integrity of these signal pathways. Embodiments mill the bottom of the PCB to form a variable-depth cavity. The different milling depths of the variable-depth cavity are selected to remove the stub portions of the plurality of vias and the dielectric material between the stubs. By configuring the PCB power planes as the topmost trace layers, decoupling capacitors may be located at the greatest depth of the variable-depth cavity, thus reducing the loop inductance in the power circuit of the PCB.

Abstract: In accordance with embodiments of the present disclosure, a connector may include a housing and an electrically-conductive pin housed in the housing and configured to electrically couple to a corresponding electrically-conductive conduit of an information handling resource comprising the connector. The pin may include a beam extending from the housing and a stub terminating the pin, the stub having a per-unit-length surface area greater than that of the beam.

Abstract: A dual axial cable is provided with adjacent and substantially parallel first and second wires. Each wire is formed from electrical conductor surrounded by a respective first and second electrical insulator having lengthwise drain alignment groove on outward side and having respective first and second inward sides of interlocking structure. First and second inward sides of interlocking structure of first and second electrical insulators mutually engage to prevent relative transverse displacement of first and second wires. The interlocking structure maintains the planar alignment of lengthwise drain alignment grooves and electrical conductors of first and second wires. First and second drain conductors are received respectively in lengthwise drain alignment grooves of first and second electrical insulators and run adjacent and substantially parallel to first and second electrical conductors. Drain conductors are maintained in parallel alignment to electrical conductors to provide shielding benefits.

Abstract: In accordance with some embodiments of the present disclosure, a connector may include a housing and a pin housed in the housing and configured to electrically couple to a corresponding electrically-conductive conduit of a device comprising the connector. A body of the pin is formed of a material having a first conductivity. The pin may include a first portion between a proximal point of the pin and a medial point of the pin, and a second portion between the medial point of the pin and a distal point of the pin. The medial point of the pin is proximate to a point of electrical contact of the pin with another pin. The second portion is at least partially covered by a layer of material having a second conductivity that is lower than the first conductivity.

Abstract: A cable includes first and second electrically conducting wires, each of the two wires surrounded by a respective isolating dielectric material for a length of the respective wire. A signal propagation skew between the first and second wires may be detected, and a dielectric constant associated with a wire may be changed to mitigate the detected signal propagation skew. The dielectric constant may be changed by removing or adding dielectric material from or to the wire.

Abstract: A cable assembly includes a printed circuit board having a first surface and a second surface. A first post and a second post extend from one side of the printed circuit board. A first signal pad, a second signal pad, and a first ground pad are each coupled to the first surface. A first cable has a first signal wire at least partially covered by a first insulator and a second signal wire at least partially covered by a second insulator. The first cable further has a first ground shield at least partially covering the first and second insulators. A first end of a first cable is mounted between the first and second posts. A conductive attachment couples the first ground shield to the first ground pad.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

Abstract: The present invention relates to compounds of the general form (I). The present invention relates to new substituted diazepino-indole derivatives of the general formula (I), and to pharmaceutically acceptable salts thereof, as well as to pharmaceutical compositions comprising such compounds, to new intermediate thereof, as well as to the use of such compounds in treatment or prevention of disorders associated with melanin-concentrating hormone receptor 1 activity.

Abstract: An information handling system includes an information handling subsystem, a power supply unit operably connected to the information handling subsystem, and a battery power subsystem operably connected to the information handling subsystem and having a controller. The controller configured to enter a learning mode of the battery power subsystem when the information handling subsystem is in a normal power state, enable a regulator output of a regulator of the battery power subsystem to provide power from a battery of the battery power subsystem at a learning mode current limit and at a learning mode voltage level to the information handling subsystem, provide, via the regulator output, power from the battery at a constant learning mode current level and at the learning mode voltage level to the information handling subsystem, and determine that the battery has been discharged to an acceptable discharge level.

Abstract: A board adapter system includes a first adapter board. A secondary first processor coupling is located on the first adapter board, and the first adapter board passes signals between a primary first processor coupling on a first board and a first processor coupled to the secondary first processor coupling when the first adapter board engages the primary first processor coupling. A first/third processor communication bus extends between the secondary first processor coupling and the second board connector on the first adapter board, and passes signals between the first processor and a third processor that is coupled to the second board connector. A first/fourth processor communication bus extends between the secondary first processor coupling and the second board connector, and passes signals between the first processor and a fourth processor that is coupled to the second board connector on the first adapter board.

Abstract: Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A cable includes first and second electrically conducting wires, each of the two wires surrounded by a respective isolating dielectric material for a length of the respective wire. A signal propagation skew between the first and second wires may be detected, and a dielectric constant associated with a wire may be changed to mitigate the detected signal propagation skew. The dielectric constant may be changed by removing or adding dielectric material from or to the wire.

Abstract: An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A connector includes a wafer having first, second, third, and fourth communication channels. The first and second communication channels form a first differential pair, and the third and fourth communication channels form a second differential pair. The wafer includes a plug and a receptacle. The plug includes a first portion of the first, second, third, and fourth communication channels. The receptacle includes a second portion of the first, second, third, and fourth communication channels. A first crisscross is located at a first predetermined location of the first and second communication channels of the first differential pair. The first crisscross changes a first polarity of a first signal to be transmitted on the first differential pair. A second polarity of a second signal to be transmitted on the second differential pair remains the same throughout an entire length of the second differential pair.