Patents by Inventor Sandor Farkas

Sandor Farkas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10111334
    Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 23, 2018
    Assignee: Dell Products, L.P.
    Inventors: Kevin W. Mundt, Sandor Farkas, Bhyrav M. Mutnury, Yeshaswy Rajupalepu
  • Publication number: 20180294076
    Abstract: A cable assembly includes a printed circuit board having a first surface and a second surface. A first post and a second post extend from one side of the printed circuit board. A first signal pad, a second signal pad, and a first ground pad are each coupled to the first surface. A first cable has a first signal wire at least partially covered by a first insulator and a second signal wire at least partially covered by a second insulator. The first cable further has a first ground shield at least partially covering the first and second insulators. A first end of a first cable is mounted between the first and second posts. A conductive attachment couples the first ground shield to the first ground pad.
    Type: Application
    Filed: April 6, 2017
    Publication date: October 11, 2018
    Inventors: SANDOR FARKAS, BHYRAV M. MUTNURY
  • Publication number: 20180288876
    Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: KEVIN W. MUNDT, SANDOR FARKAS, BHYRAV M. MUTNURY, YESHASWY RAJUPALEPU
  • Patent number: 10055127
    Abstract: An operational parameter is accessed at a data storage device. The operational parameter is encoded using a serial data protocol. The encoded operational parameter is superimposed on an activity indicator signal outputted by the data storage device. The activity indicator signal is configured to be coupled to a light emitting diode.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: August 21, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Kevin W. Mundt, Sandor Farkas
  • Publication number: 20180220527
    Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 2, 2018
    Inventors: Stuart Allen Berke, Sandor Farkas, Bhyrav M. Mutnury
  • Patent number: 9985360
    Abstract: An electrical connector may be used to connect and propagate signals between electrical systems, devices, and components. The electrical connector may comprise a male conductor component with one or more contacts positioned on a member. The electrical connector may comprise a female conductor component configured to be a receptacle for receiving a portion of the male conductor and having one or more moveable conduction arms which may be actuated to contact respective one or more contacts positioned on the member of the male conductor component.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 29, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Raymond D. Heistand, II, Sandor Farkas, Bhyrav Mutnury
  • Patent number: 9955568
    Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 24, 2018
    Assignee: Dell Products, LP
    Inventors: Stuart Allen Berke, Sandor Farkas, Bhyrav M. Mutnury
  • Publication number: 20180093989
    Abstract: The present invention relates to compounds of the general form (I). The present invention relates to new substituted diazepino-indole derivatives of the general formula (I), and to pharmaceutically acceptable salts thereof as well as to pharmaceutical compositions comprising such compounds, to new intermediate thereof as well as to the use of such compounds in treatment or prevention of disorders associated with melanin-concentrating hormone receptor 1 activity.
    Type: Application
    Filed: April 14, 2016
    Publication date: April 5, 2018
    Inventors: Gyula BEKE, János ÉLES, András BOROS, Sándor FARKAS, György Miklós KESERÜ
  • Publication number: 20180090243
    Abstract: A dual axial cable includes first and second signal conductors, a shield, and a drain wire. The first and second signal conductors transmit a differential signal. The shield is spirally wrapped around the first and second conductors, and causes a resonant characteristic of the dual axial cable. The drain wire provides a return path for the differential signal in the dual axial cable. The drain wire is roughened to a specific amount of roughness, which reduces signal loss at resonant frequencies of the resonant characteristic caused by the shield.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Sandor Farkas, Stuart Allen Berke, Bhyrav M. Mutnury
  • Publication number: 20180062320
    Abstract: A connector includes a wafer having first, second, third, and fourth communication channels. The first and second communication channels form a first differential pair, and the third and fourth communication channels form a second differential pair. The wafer includes a plug and a receptacle. The plug includes a first portion of the first, second, third, and fourth communication channels. The receptacle includes a second portion of the first, second, third, and fourth communication channels. A first crisscross is located at a first predetermined location of the first and second communication channels of the first differential pair. The first crisscross changes a first polarity of a first signal to be transmitted on the first differential pair. A second polarity of a second signal to be transmitted on the second differential pair remains the same throughout an entire length of the second differential pair.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Raymond DeWine Heistand, II, Sandor Farkas, Bhyrav M. Mutnury
  • Patent number: 9867295
    Abstract: Systems and methods for providing a ball grid array connection include providing a circuit board having a circuit board surface including a plurality of pads. A ball grid array component includes a plurality of solder balls. The ball grid array component is coupled to the circuit board to position each of the plurality of solder balls adjacent a respective one of the plurality of pads. A solder reflow process is then performed to produce a plurality of soldered connections from each of the plurality of solder balls and a respective one of the plurality of pads. At least one spacer member is provided between the ball grid array component and the circuit board during the solder reflow process to provide a mechanical stop between the ball grid array component and the circuit board and a minimum height for each of the plurality of soldered connections.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: January 9, 2018
    Assignee: Dell Products L.P.
    Inventors: Bhavesh Patel, Sandor Farkas, Wallace Huson Ables
  • Patent number: 9781825
    Abstract: A flex circuit including a plurality of layers folded on a first fold line and folded on a second fold line is disclosed. The plurality of layers may include a first conductive layer, an insulating layer adjacent the first conductive layer, and a second conductive layer adjacent the insulating layer. The flex circuit may include a plurality of slits extending through each layer of the plurality of layers, the plurality of slits disposed on the first fold line and the second fold line.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: October 3, 2017
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Girish Kumar Singh, Bhyrav M. Mutnury
  • Patent number: 9768555
    Abstract: In accordance with embodiments of the present disclosure, a connector may include a housing and a pin housed in the housing and configured to electrically couple to a corresponding electrically-conductive conduit of an information handling resource comprising the connector. The pin may include an approximate connection point at which the pin electrically couples to a corresponding pin of another connector mated to the connector and a stub extending from the approximate connection point and constructed such that a per-unit-length signal propagation delay through the stub is significantly larger than a per-unit-length signal propagation delay through the remainder of the pin excluding the stub.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: September 19, 2017
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Bhyrav M. Mutnury, Raymond Dewine Heistand, II
  • Patent number: 9769926
    Abstract: A circuit board includes a board base with a first surface and a second surface that is located opposite the first surface. A plurality of first coupling pads are located on the first surface of the board base. A plurality of second coupling pads are located on the second surface of the board base. The first coupling pads and the second coupling pads define a coupling pad footprint. A breakout via system is included in the board base. The breakout via system includes a plurality of primary signal vias that are located in the board base and outside of the coupling pad footprint, a plurality of first primary signal via connections that extend between the primary signal vias and the plurality of first coupling pads, and a plurality of second primary signal via connections that extend between the primary signal vias and the plurality of second coupling pads.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 19, 2017
    Assignee: Dell Products L.P.
    Inventors: Kevin Warren Mundt, Sandor Farkas, Bhyrav Mutnury
  • Publication number: 20170264040
    Abstract: In accordance with embodiments of the present disclosure, a connector may include a housing and an electrically-conductive pin housed in the housing and configured to electrically couple to a corresponding electrically-conductive conduit of an information handling resource comprising the connector. The pin may include a beam extending from the housing and a stub terminating the pin, the stub having a per-unit-length surface area greater than that of the beam.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 14, 2017
    Applicant: Dell Products L.P.
    Inventors: Sandor Farkas, Bhyrav M. Mutnury, Raymond Dewine Heistand, II
  • Publication number: 20170231091
    Abstract: Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 10, 2017
    Applicant: Dell Products, L.P.
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Sandor Farkas
  • Publication number: 20170231099
    Abstract: An electrical break is created in a via that would ordinarily electrically connect different layers of a printed circuit board. The electrical break severs the via into two or more separate and electrically disconnected vias. The electrical break may be placed at any depth along the via, thus demarking different purposes associated with different layers.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Kevin W. Mundt, Sandor Farkas
  • Patent number: 9690358
    Abstract: A method and apparatus for system control of a central processing unit (CPU) maximum power detector are provided. In accordance with at least one embodiment, a decision is made as to whether a response of a maximum power detector of the CPU is to be altered. When the response is to be altered, a modified input level is provided to the maximum power detector to alter the response. As an example, the modified input level can prevent the maximum power detector from triggering a power throttling function. When the response is not to be altered, an existing input level for the maximum power detector is maintained. In accordance with at least one embodiment, an apparatus or information handling system can comprise a voltage regulator (VR), a current sensor, a CPU comprising a maximum power detector, and a digital to analog converter (DAC).
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 27, 2017
    Assignee: DELL PRODUCTS, LP
    Inventors: John E. Jenne, Shawn J. Dube, Sandor Farkas
  • Publication number: 20170170578
    Abstract: An electrical connector may be used to connect and propagate signals between electrical systems, devices, and components. The electrical connector may comprise a male conductor component with one or more contacts positioned on a member. The electrical connector may comprise a female conductor component configured to be a receptacle for receiving a portion of the male conductor and having one or more moveable conduction arms which may be actuated to contact respective one or more contacts positioned on the member of the male conductor component.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Raymond D. Heistand, II, Sandor Farkas, Bhyrav Mutnury
  • Patent number: 9678137
    Abstract: Methods and systems for monitoring contact joint integrity in an information handling system may include precisely monitoring a change in resistance of a resistive element associated with a contact joint. The change in resistance of the resistive element may be indicative of the integrity of the contact joint. The resistance may be measured using a modulated current source and by demodulating a voltage signal resulting from the modulated current flowing across the resistive element.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: June 13, 2017
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Sandor Farkas, Wallace H. Ables