Abstract: A method and system are provided for compensating for brightness changes in a display having an array of display pixels. The method includes storing a plurality of look-up tables, where each table has a plurality of brightness signals that provide compensation for a brightness change when the refresh rate is changed during a panel self-refresh. The method also includes using display control circuitry to determine the refresh rate associated with an input signal and to determine a compensation based on the refresh rate. The display control circuitry may, for example, use non-linear interpolation to generate a look-up table for the refresh rate. The display control circuitry may adjust the input signal based on the look-up table to produce an output signal that compensates for a brightness change at the refresh rate. The output signal may be transmitted to the array of display pixels.

Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Abstract: Methods, systems, and devices for improving contrast, dynamic range, and power consumption of a backlight in a display are provided. By way of example, a method includes receiving image data to be displayed on pixels of a display panel, generating a global histogram of the image data, generating a plurality of thresholds based on the global histogram, and defining a first threshold and a second threshold of the plurality of thresholds as local thresholds based on the global histogram and a local histogram. The first threshold and the second threshold are generated according to a local tone mapping function. The method further includes adjusting a luminance of one or more of pixels of the display panel based at least in part on the first threshold and the second threshold.

Abstract: Gate driver circuitry in a display may supply gate line signals to rows of pixels on gate lines. Data line driver circuitry may supply data line signals to columns of pixels on data lines. The gate driver circuitry may have registers that are coupled to form a shift register that supplies the gate line signals to the gate lines. To compensate for data line signal propagation delays, the registers of the shift register may be clocked with increasingly delayed clocks as a function of increasing distance away from the display driver circuitry. To compensate for gate line signal propagation delays, the data line driver circuitry may impose increasing delays on the data line signals carried on the data lines as a function of increasing distance of the data lines away from the gate driver circuitry.

Abstract: This application relates to systems, methods, and apparatus for optimizing the operations of a power converter of a display panel based on image data to be output by the display panel. The power converter can include one or more switches that can be activated or deactivated based on the image data in order to shift a power efficiency of the power converter. Power efficiency is shifted as a result of balancing an amount of charge necessary for a load with an amount of resistance created when activating switches of the power converter. Therefore, by dynamically altering a configuration of a power converter based on image data, power efficiency of the power converter can be improved.

Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.

Abstract: Methods and devices for reducing the power consumption of a frame buffer and timing controller of an electronic display are provided. By way of example, a method of operating an electronic display includes receiving image data from a processor of the electronic display, storing the image data to a buffer of the electronic display, reading the image data from the buffer to supply the image data to a column driver of the electronic display, determining whether an amount of image data stored in buffer is less than a threshold, and switching from reading the image data from the buffer to reading the image data directly from the processor when the amount of image data stored in buffer is less than the threshold.

Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Abstract: An electronic device may include a display having an array of display pixels. Storage and processing circuitry may generate display data for the display in an RGB input color space. The display may display the display data in an RGBW output color space. Display control circuitry may use sets of predetermined conversion factors to convert display data from the RGB input color space to the RGBW output color space without requiring conversion to a device-independent color space. Each set of predetermined conversion factors may be associated with a color in a set of predetermined colors. Using the sets of predetermined conversion factors, the display control circuitry may convert RGB values in the input color space to RGBW values in the output color space. The display control circuitry may supply data signals corresponding to the display data in the RGBW output color space to the array of display pixels.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Abstract: Methods and devices employing circuitry for dynamically adjusting bandwidth control of a display interface are provided. The display interface or image content is dynamically adjusted to support both high-speed image data (e.g., 120 Hz image data) and lower-speed content (e.g., 60 Hz content). For example, in some embodiments, additional pixel pipelines and/or processing lanes may be activated during the rendering of high-speed image data, but not during the rendering of low-speed image data. Additionally or alternatively, high-speed image data, but not low-speed data, may be compressed to render high-speed content over an interface that supports only low-speed content.

Abstract: Systems and methods for controlling operation of an electronic display are provided. One embodiment describes an electronic display, which includes a display driver that writes image frames to pixels of the electronic display with a first refresh rate or a second refresh rate; and a timing controller that receives a plurality of image frames from an image source, in which the plurality of image frames are displayed on the electronic display to play video content; detects a cadence with which the plurality of image frames are received from the image source; and, based at least in part on the cadence of the plurality of image frames, instructs the display driver to write each of the plurality of image frames either as a single image frame at the first refresh rate or an image frame at the first refresh rate followed by a repeat of the image frame at the second refresh rate.

Abstract: A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel. The produced internal start pulse was qualified by an output of a last cell of the gate driver shift register. Other embodiments are also described and claimed.

Abstract: One embodiment of the present disclosure describes an electronic display. The electronic display includes a display driver that write image frames to pixels of the electronic display with a first refresh rate or a second refresh rate, in which the second refresh rate is less than the first refresh rate. Additionally, the electronic display includes a timing controller that receives image frames from an image source, in which one or more of the image frames are configured to be displayed on the display panel to play video content; determines a capture rate of the video content based at least in part on a cadence with which the image frames are received, in which the capture rate describes a rate at which each of the one or more image frames was captured by an image sensor; and instructs the display driver to write the one or more of the image frames at the second refresh when the second refresh rate is an integer multiple of the capture rate.

Abstract: One embodiment describes an electronic display. The electronic display includes display driver circuitry that displays at least a first image frame and a second image frame on the electronic device using a first display pixel and a second display pixel. The electronic display also includes touch sensing circuitry that detects user interaction with the electronic display. A timing controller of the electronic display determines at least a first insertion time for a first intra-frame pause for the first image frame and a second insertion time for a second intra-frame pause for the second image frame. The first and second intra-frame pauses are periods where the display driver circuitry is pauses rendering of image data to allow the touch sensing circuitry to detect user interaction. The insertion times for the first and second intra-frame pauses are varied from one another.

Abstract: Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.

Abstract: Methods and systems for compensating for VCOM variations include determining a voltage change in pixels between frames to be displayed on an electronic display. Based on the determined voltage change, VCOM variation is calculated based on coupling the VCOM to one or more data lines of the electronic display. VCOM compensation is determined and applied to offset for the VCOM variation. Using the VCOM offset, subsequent pixel content for the one or more pixels is written using the compensated VCOM.

Abstract: One embodiment describes an electronic display that displays image frames with a first refresh rate or a second refresh rate, in which the second refresh rate is lower than the first refresh rate; a display driver that writes the image frames by applying voltage to a display panel; and a timing controller that receives first image data from an image source, in which the first image data describes a first image frame and a first desired refresh rate equal to the second fresh rate; and that instructs the display driver to apply a first set of voltage polarities to the display panel to display first image frame at the first refresh rate and to apply a second set of voltage polarities to the display the first image frame at the second refresh rate when polarity of inversion imbalance accumulated is equal to polarity of the first set of voltage polarities.

Abstract: A device includes a timing test circuit. The timing test circuit receives a timing signal related to the display of an image on a display. The timing test circuit also determines if the timing signals are invalid. Moreover, the timing test circuit transmits a fault indication when the timing signals are determined to be invalid.

Abstract: System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.