Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.

Abstract: A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N?1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N?1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.

Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.

Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.

Abstract: A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.

Abstract: A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N?1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N?1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: A semiconductor device may include a latch circuit configured for storing a row address including information on a position where a smart refresh operation has been performed, as a storage address. The semiconductor device may include a refresh control circuit configured for controlling, depending on a result of comparing a row address inputted from an exterior and the storage address, a smart refresh operation to be performed for the row address, and omitting the smart refresh operation based on the row address and the storage address being the same combination.

Abstract: A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value

Abstract: A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.

Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A semiconductor device may include a latch circuit configured for storing a row address including information on a position where a smart refresh operation has been performed, as a storage address. The semiconductor device may include a refresh control circuit configured for controlling, depending on a result of comparing a row address inputted from an exterior and the storage address, a smart refresh operation to be performed for the row address, and omitting the smart refresh operation based on the row address and the storage address being the same combination.

Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.