Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

Abstract: A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.

Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs commands, a test address, addresses and a precharge signal. The second semiconductor device enters an auto-precharge operation according to a combination of the commands after a read operation or a write operation and receives the test address and the precharge signal to perform an auto-precharge operation of one bank selected from a plurality of banks by the addresses.

Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Abstract: A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

Abstract: A control circuit may include a refresh time control circuit configured for controlling a refresh time on the basis of an area setting signal for setting a usage area of a memory. The control circuit may include an address control circuit configured for fixing at least one bit included in an external address on the basis of the area setting signal and an area mode signal and provide an internal address.

Abstract: A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.

Abstract: A calibration circuit includes a pad suitable for receiving calibration data that toggles, a calibration reference voltage generation unit suitable for generating a calibration reference voltage from a median value of the calibration data, a comparison unit suitable for outputting a comparison signal by comparing the calibration reference voltage and a reference voltage with each other, and a reference voltage generation unit suitable for generating the reference voltage which is calibrated based on the comparison signal.

Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Abstract: A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address signals; a plurality of multi-purpose registers; and a parity check unit suitable for determining a parity check result as a pass when the number of first logic values in the command/address signals corresponds to a logic value of a parity bit, determining the parity check result as a fail when the number of the first logic values does not correspond to the logic value of the parity bit, and controlling the command/address signals to be stored in the multi-purpose registers; and a function test device suitable for applying the command/address signals to the first input pins during a function test, and controlling the command/address signals such that the number of the first logic values does not correspond to the logic value of the parity bit.

Abstract: A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. The semiconductor apparatus may include a timing tuning block configured to generate delay control signals according to a phase difference of the delay-locked clock signal and the delay-locked internal command, and tune a delay time of the internal read command according to the delay control signals and generate a timing-tuned read command.

Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller receives a temperature code signal and responsively generates a mode set signal operable to adjust a level variation and a voltage variation rate of a temperature voltage signal, wherein the temperature voltage signal level varies according to temperature when a logic level combination of the temperature code signal is different from a predefined logic level combination. The semiconductor device generates the temperature voltage signal from a drivability and a resistance value set by the mode set signal. The semiconductor device generates the temperature code signal based on a comparison of the temperature voltage signal and a reference voltage signal.

Abstract: A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. The semiconductor apparatus may include a timing tuning block configured to generate delay control signals according to a phase difference of the delay-locked clock signal and the delay-locked internal command, and tune a delay time of the internal read command according to the delay control signals and generate a timing-tuned read command.

Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed to when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Abstract: A transmitter includes first to third power supply terminals, a first buffer that is electrically coupled between the first power supply terminal and the second power supply terminal and buffers and outputs a first input signal, and a second buffer that is electrically coupled between the second power supply terminal and the third power supply terminal and buffers and outputs a second input signal that is in a differential relation to the first input signal.