Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: A method and an apparatus for controlling a display in order to secure an appropriate viewing distance between a digital device and a user who is viewing the digital device is provided. Accordingly, the method determines whether an object exists within a hazardous viewing distance using a 3D camera function provided in the digital device. If it is determined that an object exists within the hazardous viewing distance, the digital device detects a face or eyes from 2D images photographed by the camera. Next, the direction of the face is determined on the basis of the detected results, and it is determined whether a user is viewing a display screen of the digital device based on the determination. If it is determined that a user is viewing a display screen of a digital device, the digital device generates a warning that the user is positioned within a hazardous viewing distance.

Abstract: An apparatus and a method for recognizing a human body in a hybrid manner are provided. The method includes calculating body information used for recognizing a human body from an input image, detecting a region of the human body in a learning-based human body recognition manner by using the calculated body information, and tracing a movement of the detected region of the human body in a modeling-based human body recognition manner. Thereby, it is possible to quickly perform more accurate and precise recognition of the human body.

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract: A cursor displaying method that re-sizes a cursor displayed in a display field while repositioning the cursor in response to a detected user gesture.

Abstract: A method of recognizing motion of an object may include periodically obtaining depth data of a first resolution and two-dimensional data of a second resolution with respect to a scene using an image capturing device, wherein the second resolution is higher than the first resolution; determining a motion tracking region by recognizing a target object in the scene based on the depth data, such that the motion tracking region corresponds to a portion of a frame and the portion includes the target object; periodically obtaining tracking region data of the second resolution corresponding to the motion tracking region; and/or analyzing the motion of the target object based on the tracking region data.

Abstract: A mobile system may comprise a three-dimensional (3D) image sensor on a first surface of the mobile system configured to perform a first sensing to detect proximity of a subject and a second sensing to recognize a gesture of the subject by acquiring distance information for the subject; and/or a display device on the first surface of the mobile system to display results of the first sensing and the second sensing. A mobile system may comprise a light source unit; a plurality of depth pixels; and/or a plurality of color pixels. The light source unit, the plurality of depth pixels, or the plurality of color pixels may be activated based on an operation mode of the mobile system.

Abstract: An image capture method performed by a depth sensor includes; emitting a first source signal having a first amplitude towards a scene, and thereafter emitting a second source signal having a second amplitude different from the first amplitude towards the scene, capturing a first image in response to the first source signal and capturing a second image in response to the second source signal, and interpolating the first and second images to generate a final image.

Abstract: A method for controlling a user interface of an apparatus to enable intuitive manipulation for an object included in an image is provided. An object with deeper depth in a rear image of the apparatus may become selectable when the user holds a user input means close to the apparatus, while an object with shallower depth in the rear image may become selectable when the user draws the user input means away from the apparatus, thereby allowing the user to intuitively select an object in the rear image.

Abstract: Methods, systems, and devices for guiding a subject back within the recognizable visual range of a multimedia system are described. According to one of the described methods, when it is determined that the target has left the recognizable range of the multimedia system, sensor information is acquired from a portable electronic device (or controller) the user has been using to control the multimedia system, and the acquired sensor information is used to determine where the user is, relative to the recognizable range. In one example, the user is asked to make a gesture with the portable electronic device, and the sensor information concerning that gesture is used to determine the user's relative location. In another example, the sensor information recorded at the time the user left the recognizable range is used to determine the user's relative location.

Abstract: A method and apparatus for extracting three-dimensional distance information from a recognition target is provided, which enables a gesture input from a user to be correctly recognized using distance information from the recognition target, and at the same time makes it possible to efficiently save power required for detection of the gesture input. The method includes determining if a recognition target exists within a predetermined range; when the recognition target exists within the predetermined range, generating a 3D image for the recognition target; and calculating a distance to the recognition target by using the 3D image.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips.

Abstract: Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

Abstract: A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.