Abstract: The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

Abstract: A delay locked loop generates an advanced clock signal synchronized with a reference clock signal. The delay locked loop includes an input buffer, a variable delay circuit, a delay compensation circuit, a phase shifter, a delay controller, a phase sensing pump and a phase inversion controller. The variable delay circuit includes a multiplicity of delay terminals. The number of enabled delay terminals is controlled by a counting signal group. In the phase shifter, the phase of an output signal of the variable delay circuit generates the advanced clock signal with a phase of the reference clock signal. When the compared phase difference is more than Π, the phase shifter inverts a delayed clock signal to generate the advanced clock signal. When the compared phase difference is less than Π, the delayed clock signal is non-inverted to be generated as the advanced clock signal.

Abstract: A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.

Abstract: Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device.

Abstract: Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. Decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals.

Abstract: A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.

Abstract: Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON1) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON1 and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device.

Abstract: Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. Decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals.

Abstract: A data input circuit for a semiconductor memory device uses an echo clock generator to reduce the clock cycle time. The echo clock is transmitted in the memory device with the data, thereby reducing the effects of clock skew and increasing the overall device operation speed. The circuit is particularly applicable to double data rate synchronous DRAM (DDR-SDRAM) circuitry.

Abstract: A semiconductor memory device achieves high speed operation while operating at a low power supply voltage by boosting the voltage level at the plate node of a memory cell during an access operation. The memory device includes a plate voltage generator which generates a variable voltage level. The plate voltage generator includes a pair of switches for coupling the plate node to either a conventional (1/2)VCC voltage generator or a power supply node in response to a control signal. The plate voltage generator also includes a pulse generator that generates a pulse signal for controlling the switches in response to the control signal. During a precharge period, the bitline pair is charged to VCC. The plate voltage generator charges the plate node to (1/2)VCC during the precharge state and then to VCC during an access operation. This boosts the voltage level at the storage node of the memory cell, thereby decreasing the time required to amplify the signals on the bitlines.

Abstract: Self repairing integrated circuit memory devices include the plurality of normal memory cells, plurality of spare memory cells and a plurality of spare substituting circuits. A spare substituting circuit is responsive to a defective normal memory cell address which is programmed therein, to substitute at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein. A sequential spare substituting circuit selector is connected to the spare substituting circuits and is responsive to a defect indication signal, to sequentially select a respective one of the spare circuits for programming with sequential ones of the defective normal memory cell addresses. An alarm signal is generated if all of the spare substituting circuits have been used. If a defect is present in at least two normal memory cells in different rows and the same column, a spare column is substituted rather than two spare rows.

Abstract: Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g.

Abstract: A bit line sensing circuit of a semiconductor memory device having NMOS and PMOS sense amps connected to a bit line includes a variable delay path for variably controlling an interval of the operating time between the NMOS and PMOS sense amps in response to a power voltage sensing signal generated by sensing a power voltage level.