Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.

Abstract: A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

Abstract: A memory controller includes a command input unit suitable for receiving a write command, a read command, and a send command, a command counting unit suitable for performing a counting operation in response to the write command to produce a counted data, a first Error Correction Code (ECC) encoding unit suitable for performing a first ECC encoding onto a data that is read from a memory device in response to the read command to produce a first ECC encoded data, a second ECC encoding unit suitable for performing a second ECC encoding onto the counted data in response to the send command to produce a second ECC encoded data, and a data output unit suitable for combining the first ECC encoded data and the second ECC encoded data to output a read data.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: Disclosed is a memory system includes a memory device including a plurality of memory blocks, a write operation management circuit configured to update write operation counts for the plurality of memory blocks, a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks, a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block, and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: The memory system includes a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host, a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the BCH error correction code, and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: A circuit for calculating power consumption of a phase change memory (PCM) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. The plurality of pipelines may be configured to correspond to a plurality of write periods exhibiting different power consumption values during a write operation of the PCM device executed by a write command. The plurality of pipelines may shift or transmit data in synchronization with a clock signal. The arithmetic logic circuit may be configured to perform an adding operation of all of deviations of the power consumption values at a point of time that data transmission between at least two of the plurality of pipelines occurs, to thus generate a total power consumption value.

Abstract: A circuit for calculating power consumption of a phase change memory (PCM) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. The plurality of pipelines may be configured to correspond to a plurality of write periods exhibiting different power consumption values during a write operation of the PCM device executed by a write command. The plurality of pipelines may shift or transmit data in synchronization with a clock signal. The arithmetic logic circuit may be configured to perform an adding operation of all of deviations of the power consumption values at a point of time that data transmission between at least two of the plurality of pipelines occurs, to thus generate a total power consumption value.

Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Abstract: A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. The detector may generate an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data is equal to or more than the reference value.

Abstract: A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.

Abstract: A memory device may include a memory cell array having a plurality of memory cells, and a controller suitable for reading data of a memory cell corresponding to an address of write data, among the memory cells, and comparing the write data and the read data to check specific bits different from corresponding bits of the read data, among a plurality of bits of the write data, according to a write operation request. The controller may output a check result to outside after a preset time from the write operation request.

Abstract: A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. The detector may generate an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data is equal to or more than the reference value.

Abstract: An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.

Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.