Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: A semiconductor device includes at least one normal block suitable for storing normal data; at least one sample block suitable for storing sample data; a phenomenon analysis block suitable for generating at least one phenomenon analysis signal based on the sample data; and a control block suitable for controlling a level of reference data required when the normal data are read based on the at least one phenomenon analysis signal.

Abstract: The memory system includes a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host, a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the BCH error correction code, and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.

Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.

Abstract: A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

Abstract: A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: A semiconductor system includes a medium controller and a semiconductor module. The medium controller outputs an address that is sequentially counted in a test mode, senses levels of data corresponding to the address in the test mode to determine if the data has a row error or a chip error, and changes a combination of a host address to generate and store a spare address if a combination of the address corresponds to the chip error in the test mode. The semiconductor module includes a plurality of semiconductor devices. The semiconductor module repairs the address to output the data from a redundancy area if a combination of the address corresponds to the row error. The semiconductor module outputs the data from a spare area selected by the spare address if a combination of the address corresponds to the chip error.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. The semiconductor system may include a second semiconductor device configured for storing the transmission address in a lookup table circuit when the error flag signal is enabled, and comparing the transmission address and a storage address stored in the lookup table circuit when the read operation is performed based on the transmission command and outputting the transmission data from the lookup table circuit.

Abstract: An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.

Abstract: A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A method for operating a memory device comprising a plurality of memory cells, the method may include: performing a first refresh operation comprising sequentially applying a recovery pulse to each of the plurality of memory cells and repeating the sequential application of the recovery pulse to each of the plurality of memory cells for a predetermined number of times; and performing a second refresh operation comprising sequentially re-writing data of each of the plurality of memory cells once after the first refresh operation is performed for the predetermined number of times.

Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Abstract: A method for operating a memory device comprising a plurality of memory cells, the method may include: performing a first refresh operation comprising sequentially applying a recovery pulse to each of the plurality of memory cells and repeating the sequential application of the recovery pulse to each of the plurality of memory cells for a predetermined number of times; and performing a second refresh operation comprising sequentially re-writing data of each of the plurality of memory cells once after the first refresh operation is performed for the predetermined number of times.

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

Abstract: A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.