Patents by Inventor Sang-Hoon Cho
Sang-Hoon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10879461Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: GrantFiled: December 5, 2019Date of Patent: December 29, 2020Assignee: SK hynix Inc.Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
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Patent number: 10863864Abstract: The present invention relates to a water and oil type fryer minimizing the transfer of heat from a layer of oil for frying to a water layer, the water and oil type fryer comprising: an oil cask for frying having a connection pipe having a predetermined cross-sectional area ratio; a gas burner supplying heat to a heating flow path, or an electric heater directly supplying heat to oil for frying; a container for cleaning having a drain pipe, and simultaneously accommodating oil which is connected with oil in the oil cask through the connection pipe, and water which forms a boundary with the oil; and a sediment layer discharge pipe positioned below a boundary surface of oil and water.Type: GrantFiled: May 7, 2015Date of Patent: December 15, 2020Inventor: Sang Hoon Cho
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Patent number: 10827510Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.Type: GrantFiled: June 24, 2019Date of Patent: November 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hoo Park, Sang-Hoon Cho, Geon-Soo Kim
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Publication number: 20200111956Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Hyo June KIM, Chi Ho KIM, Sang Hoon CHO, Eung Rim HWANG
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Patent number: 10535819Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: GrantFiled: March 30, 2018Date of Patent: January 14, 2020Assignee: SK HYNIX INC.Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
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Publication number: 20190313421Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.Type: ApplicationFiled: June 24, 2019Publication date: October 10, 2019Inventors: Dong-Hoo PARK, Sang-Hoon CHO, Geon-Soo KIM
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Patent number: 10381410Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.Type: GrantFiled: November 1, 2018Date of Patent: August 13, 2019Assignee: SK HYNIX INC.Inventors: Chi-Ho Kim, Eung-Rim Hwang, Sang-Hoon Cho
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Publication number: 20190221612Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.Type: ApplicationFiled: November 1, 2018Publication date: July 18, 2019Inventors: Chi-Ho KIM, Eung-Rim HWANG, Sang-Hoon CHO
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Patent number: 10334607Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.Type: GrantFiled: May 21, 2015Date of Patent: June 25, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hoo Park, Sang-Hoon Cho, Geon-Soo Kim
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Publication number: 20190088871Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: ApplicationFiled: March 30, 2018Publication date: March 21, 2019Inventors: Hyo June KIM, Chi Ho KIM, Sang Hoon CHO, Eung Rim HWANG
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Publication number: 20180177338Abstract: The present invention relates to a water and oil type fryer minimizing the transfer of heat from a layer of oil for frying to a water layer, the water and oil type fryer comprising: an oil cask for frying having a connection pipe having a predetermined cross-sectional area ratio; a gas burner supplying heat to a heating flow path, or an electric heater directly supplying heat to oil for frying; a container for cleaning having a drain pipe, and simultaneously accommodating oil which is connected with oil in the oil cask through the connection pipe, and water which forms a boundary with the oil; and a sediment layer discharge pipe positioned below a boundary surface of oil and water.Type: ApplicationFiled: May 7, 2015Publication date: June 28, 2018Inventor: Sang Hoon CHO
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Publication number: 20150351111Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of 5 communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.Type: ApplicationFiled: May 21, 2015Publication date: December 3, 2015Inventors: Dong-Hoo PARK, Sang-Hoon CHO, Geon-Soo KIM
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Patent number: 8759233Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.Type: GrantFiled: June 21, 2012Date of Patent: June 24, 2014Assignee: Hynix Semiconductor Inc.Inventor: Sang Hoon Cho
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Publication number: 20130157383Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.Type: ApplicationFiled: June 21, 2012Publication date: June 20, 2013Inventor: Sang Hoon CHO
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Patent number: 8294207Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.Type: GrantFiled: June 24, 2011Date of Patent: October 23, 2012Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Cho, Yun-Seok Cho, Myung-Ok Kim, Sang-Hoon Park, Young-Kyun Jung
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Publication number: 20110254081Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.Type: ApplicationFiled: June 24, 2011Publication date: October 20, 2011Applicant: Hynix Semiconductor Inc.Inventors: Sang-Hoon CHO, Yun-Seok CHO, Myung-Ok KIM, Sang-Hoon PARK, Young-Kyun JUNG
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Patent number: 8030205Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.Type: GrantFiled: November 13, 2009Date of Patent: October 4, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hae-Jung Lee, Sang-Hoon Cho, Suk-Ki Kim
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Patent number: 7989292Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.Type: GrantFiled: December 12, 2008Date of Patent: August 2, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Cho, Yun-Seok Cho, Myung-Ok Kim, Sang-Hoon Park, Young-Kyun Jung
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Patent number: 7985667Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.Type: GrantFiled: June 26, 2009Date of Patent: July 26, 2011Assignee: Hynix Semiconductor Inc.Inventor: Sang-Hoon Cho
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Patent number: RE44473Abstract: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.Type: GrantFiled: February 27, 2012Date of Patent: September 3, 2013Assignee: Hynix Semiconductor Inc.Inventor: Sang-Hoon Cho