Patents by Inventor Sang-Hoon Cho

Sang-Hoon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879461
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
  • Patent number: 10863864
    Abstract: The present invention relates to a water and oil type fryer minimizing the transfer of heat from a layer of oil for frying to a water layer, the water and oil type fryer comprising: an oil cask for frying having a connection pipe having a predetermined cross-sectional area ratio; a gas burner supplying heat to a heating flow path, or an electric heater directly supplying heat to oil for frying; a container for cleaning having a drain pipe, and simultaneously accommodating oil which is connected with oil in the oil cask through the connection pipe, and water which forms a boundary with the oil; and a sediment layer discharge pipe positioned below a boundary surface of oil and water.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: December 15, 2020
    Inventor: Sang Hoon Cho
  • Patent number: 10827510
    Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoo Park, Sang-Hoon Cho, Geon-Soo Kim
  • Publication number: 20200111956
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Hyo June KIM, Chi Ho KIM, Sang Hoon CHO, Eung Rim HWANG
  • Patent number: 10535819
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 14, 2020
    Assignee: SK HYNIX INC.
    Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
  • Publication number: 20190313421
    Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Dong-Hoo PARK, Sang-Hoon CHO, Geon-Soo KIM
  • Patent number: 10381410
    Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 13, 2019
    Assignee: SK HYNIX INC.
    Inventors: Chi-Ho Kim, Eung-Rim Hwang, Sang-Hoon Cho
  • Publication number: 20190221612
    Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.
    Type: Application
    Filed: November 1, 2018
    Publication date: July 18, 2019
    Inventors: Chi-Ho KIM, Eung-Rim HWANG, Sang-Hoon CHO
  • Patent number: 10334607
    Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoo Park, Sang-Hoon Cho, Geon-Soo Kim
  • Publication number: 20190088871
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Application
    Filed: March 30, 2018
    Publication date: March 21, 2019
    Inventors: Hyo June KIM, Chi Ho KIM, Sang Hoon CHO, Eung Rim HWANG
  • Publication number: 20180177338
    Abstract: The present invention relates to a water and oil type fryer minimizing the transfer of heat from a layer of oil for frying to a water layer, the water and oil type fryer comprising: an oil cask for frying having a connection pipe having a predetermined cross-sectional area ratio; a gas burner supplying heat to a heating flow path, or an electric heater directly supplying heat to oil for frying; a container for cleaning having a drain pipe, and simultaneously accommodating oil which is connected with oil in the oil cask through the connection pipe, and water which forms a boundary with the oil; and a sediment layer discharge pipe positioned below a boundary surface of oil and water.
    Type: Application
    Filed: May 7, 2015
    Publication date: June 28, 2018
    Inventor: Sang Hoon CHO
  • Publication number: 20150351111
    Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of 5 communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.
    Type: Application
    Filed: May 21, 2015
    Publication date: December 3, 2015
    Inventors: Dong-Hoo PARK, Sang-Hoon CHO, Geon-Soo KIM
  • Patent number: 8759233
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Hoon Cho
  • Publication number: 20130157383
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
    Type: Application
    Filed: June 21, 2012
    Publication date: June 20, 2013
    Inventor: Sang Hoon CHO
  • Patent number: 8294207
    Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 23, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hoon Cho, Yun-Seok Cho, Myung-Ok Kim, Sang-Hoon Park, Young-Kyun Jung
  • Publication number: 20110254081
    Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Hoon CHO, Yun-Seok CHO, Myung-Ok KIM, Sang-Hoon PARK, Young-Kyun JUNG
  • Patent number: 8030205
    Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: October 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Jung Lee, Sang-Hoon Cho, Suk-Ki Kim
  • Patent number: 7989292
    Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 2, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hoon Cho, Yun-Seok Cho, Myung-Ok Kim, Sang-Hoon Park, Young-Kyun Jung
  • Patent number: 7985667
    Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: July 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Hoon Cho
  • Patent number: RE44473
    Abstract: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: September 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Hoon Cho