Abstract: An electronic device and a wireless network access method in the electronic device. The wireless network access method includes obtaining at least one of wireless network access information associated with a wireless network that is capable of 5 communicating with the electronic device and effectiveness information. The at least one of network access information and effectiveness information is transmitted information to an external device with respect to the electronic device such that the external device determines whether to access the wireless network or to release the access to the wireless network based on the received at least one information.

Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.

Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.

Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.

Abstract: In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bulb-shaped recesses in a substrate, forming a gate insulation layer over the substrate including the bulb-shaped recesses, forming a patterned first conductive layer over sidewalls of a bulb pattern of the corresponding bulb-shaped recesses, and forming a patterned second conductive layer over the gate insulation layer while filling the bulb-shaped recesses.

Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.

Abstract: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.

Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

Abstract: A method for fabricating a magnetic tunnel junction device includes forming an insulation layer having a plurality of openings, forming a first electrode over the bottom and the sidewall of an opening of the plurality of openings, forming a magnetic tunnel junction layer over the first electrode, and forming a second electrode over the magnetic tunnel junction layer to fill the remaining openings.

Abstract: In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.

Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

Abstract: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.

Abstract: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.