Patents by Inventor Sang-Hyeop Lee
Sang-Hyeop Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120049386Abstract: A semiconductor package includes a package substrate, a semiconductor chip, an insulating layer pattern, conductive connecting members and a contact-preventing member. The semiconductor chip is arranged on an upper surface of the package substrate. The semiconductor chip has bonding pads. The insulating layer pattern is formed on the semiconductor chip to expose the bonding pads. The conductive connecting members electrically connect the bonding pads with the package substrate. The contact-preventing member covers an edge portion of the semiconductor chip to prevent a contact between the conductive connecting members and the semiconductor chip. Thus, the conductive connecting members do not make contact with the semiconductor chip.Type: ApplicationFiled: July 19, 2011Publication date: March 1, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Hyung-Geun OH, Chan-Suk LEE, Sang-Hyeop LEE
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Patent number: 7988873Abstract: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region to another predetermined thickness. While the inorganic mask layer is etched in the first and second region, an organic mask layer is exposed in the third region. The organic mask layer exposed in the third region is removed to form a mask pattern. Consequently, double exposure is performed using the organic mask layer and the inorganic mask layer, so that a fine feature size that closely follows a desired layout can be formed, damage to the organic mask layer by ashing is prevented, and adhesiveness between the organic mask layer and the inorganic mask layer can be improved.Type: GrantFiled: June 26, 2007Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-Soo Kim, Sang-Hyeop Lee
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Patent number: 7414303Abstract: The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.Type: GrantFiled: March 11, 2005Date of Patent: August 19, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyeop Lee, Se-Yong Oh, Jin-Ho Kim, Chan-Suk Lee, Min-Keun Kwak, Sung-Hwan Yoon, Tae-Duk Nam
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Publication number: 20070298616Abstract: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region to another predetermined thickness. While the inorganic mask layer is etched in the first and second region, an organic mask layer is exposed in the third region. The organic mask layer exposed in the third region is removed to form a mask pattern. Consequently, double exposure is performed using the organic mask layer and the inorganic mask layer, so that a fine feature size that closely follows a desired layout can be formed, damage to the organic mask layer by ashing is prevented, and adhesiveness between the organic mask layer and the inorganic mask layer can be improved.Type: ApplicationFiled: June 26, 2007Publication date: December 27, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyong-Soo KIM, Sang-Hyeop LEE
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Publication number: 20070007634Abstract: A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.Type: ApplicationFiled: September 7, 2006Publication date: January 11, 2007Inventors: Cheul-Joong Youn, Sang-Yeop Lee, Sang-Hyeop Lee
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Patent number: 7148080Abstract: A method for joining lead frames in a chip stack package or a package stack, a chip stack package, and a method of forming a chip stack package. A joining mediator is formed on joining portions of at least one lead frame. The joining mediator has an anti-oxidation property and an inter-metallic diffusion property, and may be formed of gold wires, gold bumps, gold bars, solder bumps, solder, or solder bars. By clamping or compressing the lead frames under heat and pressure, the joining mediator forms an inter-metallic joint layer that reliably interconnects the lead frames at the joining portions.Type: GrantFiled: March 7, 2003Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Pyoung Wan Kim, Sang Hyeop Lee, Chang Cheol Lee, Gun Ah Lee
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Publication number: 20060151878Abstract: Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive plating layer. The plating unit and reflow unit may be disposed in a single line with the plating module. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.Type: ApplicationFiled: January 6, 2006Publication date: July 13, 2006Inventors: Se-Young Jeong, Nam-Seog Kim, Sung-Ki Lee, Hee-Kook Choi, Ki-Kwon Jeong, Tae-Sung Park, Yoshikuni Nakadaira, Sang-Hyeop Lee, Sung-Hwan Kim
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Publication number: 20050242417Abstract: A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.Type: ApplicationFiled: December 2, 2004Publication date: November 3, 2005Inventors: Cheul-Joong Youn, Sang-Yeop Lee, Sang-Hyeop Lee
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Publication number: 20050212099Abstract: The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.Type: ApplicationFiled: March 11, 2005Publication date: September 29, 2005Inventors: Sang-Hyeop Lee, Se-Yong Oh, Jing-Ho Kim, Chan-Suk Lee, Min-Keun Kwak, Sung-Hwan Yoon, Tae-Duk Nam
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Patent number: 6876029Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.Type: GrantFiled: August 5, 2003Date of Patent: April 5, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
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Publication number: 20040178514Abstract: A first semiconductor chip is attached to a first side of a printed circuit board, and a second semiconductor chip is attached to a second side of the printed circuit board opposite the first side of the printed circuit board. A mold is then used to form a first mold cavity which contains the first semiconductor chip over the first side of the printed circuit board, and to form a second mold cavity which contains the second semiconductor chip over the second side of the printed circuit board. The first and second mold cavities are simultaneously filled with a fill material via a mold inlet, where the mold inlet is at least partially defined through an aperture in the printed circuit board from the first side to the second side.Type: ApplicationFiled: September 22, 2003Publication date: September 16, 2004Inventors: Sang-Hyeop Lee, Hee-Kook Choi
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Publication number: 20040158978Abstract: Provided are a molding method for encapsulating in a substantially simultaneous manner wafer level packages (WLPs) arranged on opposite sides of a PCB module and a mold suitable for practicing the molding method. A PCB module is secured between an upper mold and a lower mold that cooperate to form a single mold. The upper mold includes an upper cavity for receiving an upper WLP and an upper gate through which an epoxy molding compound (EMC) may be forced into the upper cavity. The lower mold includes a lower cavity for receiving a lower WLP and a lower gate through which EMC may be forced into the lower cavity. The EMC may enter the gates through a single inlet formed between upper and lower inlet forming blocks, thereby encapsulating both the upper and lower sides of the PCB module substantially simultaneously, thereby improving productivity.Type: ApplicationFiled: February 6, 2004Publication date: August 19, 2004Inventors: Sang-Hyeop Lee, Hee-Kook Choi, Cheol-Joon Yoo
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Publication number: 20040033662Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.Type: ApplicationFiled: August 5, 2003Publication date: February 19, 2004Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
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Publication number: 20040014257Abstract: A method for joining lead frames in a chip stack package or a package stack, a chip stack package, and a method of forming a chip stack package. A joining mediator is formed on joining portions of at least one lead frame. The joining mediator has an anti-oxidation property and an inter-metallic diffusion property, and may be formed of gold wires, gold bumps, gold bars, solder bumps, solder, or solder bars. By clamping or compressing the lead frames under heat and pressure, the joining mediator forms an inter-metallic joint layer that reliably interconnects the lead frames at the joining portions.Type: ApplicationFiled: March 7, 2003Publication date: January 22, 2004Inventors: Pyoung Wan Kim, Sang Hyeop Lee, Chang Cheol Lee, Gun Ah Lee
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Patent number: 6624069Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.Type: GrantFiled: December 12, 2000Date of Patent: September 23, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
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Patent number: 6573168Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.Type: GrantFiled: May 25, 2001Date of Patent: June 3, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-soo Kim, Chang-woong Chu, Dong-hyun Kim, Yong-chul Oh, Hyoung-joon Kim, Byeong-yun Nam, Kyung-won Park, Sang-hyeop Lee
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Publication number: 20020001889Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.Type: ApplicationFiled: May 25, 2001Publication date: January 3, 2002Inventors: Ji-Soo Kim, Chang-Woong Chu, Dong-Hyun Kim, Yong-Chul Oh, Hyoung-Joon Kim, Beyeong-Yun Nam, Kyung-Won Park, Sang-Hyeop Lee
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Publication number: 20010001501Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.Type: ApplicationFiled: December 12, 2000Publication date: May 24, 2001Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
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Patent number: 6218260Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.Type: GrantFiled: March 6, 1998Date of Patent: April 17, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
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Patent number: 6077573Abstract: A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.Type: GrantFiled: May 22, 1998Date of Patent: June 20, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Kim, Sang-hyeop Lee, Seung-hwan Lee, Young-wook Park, Mikio Takagi