Abstract: A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.

Abstract: A semiconductor device package is equipped with devices for preventing the formulation of air traps in its encapsulated package body. These devices include dummy block leads formed on the outermost inner lead of each row of inner leads, and extended portions formed on each tie bar. Each dummy block lead extends from the end of an outermost inner lead and is integrally formed therewith. The tie bar extended portions are separated into several parts defined by spaces between the parts, and the several parts are formed integral with each other and with the tie bar. The dummy block leads and the tie bar extended portions may be formed so as to be inclined relative to horizontal and with jagged edges at their side surfaces. The dummy block leads and tie bar extended portions serve to reduce the velocity of the potting resin which forms the encapsulate, as it enters the die cavity for encapsulation, but before the resin actually contacts the chip or the inner leads.