Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract: A device includes at least one first amplifier circuit configurable to receive and amplify an input radio frequency (RF) signal having a first carrier at a first input signal level and provide a first amplified RF signal, and at least one second amplifier circuit configurable to receive and amplify the input RF signal having a second carrier at a second input signal level and provide a second amplified RF signal, the at least one first amplifier circuit having a first input impedance, the at least one second amplifier circuit having a second input impedance.

Abstract: A device includes an amplifier circuit comprising a plurality of amplification paths, and at least one switchable bypass capacitance coupled to an associated shared power distribution network, the at least one switchable bypass capacitance and at least one of the plurality of amplification paths responsive to a control signal configured to selectively ground the at least one switchable bypass capacitance and selectively enable the at least one of the amplification paths based on a selected operating mode.

Abstract: A device includes a first amplifier circuit coupled to a first transformer and a second transformer, the first transformer selectively coupled to a first shared power distribution network through a first switch, the second transformer selectively coupled to a second shared power distribution network through a second switch.

Abstract: An apparatus includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit has a first output coupled to a first load circuit in a multi-output mode, and the second amplifier circuit has a second output coupled to a second load circuit in the multi-output mode. The apparatus further includes a first divert circuit and a second divert circuit. The first divert circuit is configured to divert a first portion of a first amplified signal from the first amplifier circuit to the second load circuit in the multi-output mode. The second divert circuit is configured to divert a first portion of a second amplified signal from the second amplifier circuit to the first load circuit in the multi-output mode.

Abstract: A device includes an amplifier circuit comprising a plurality of amplification paths, and at least one switchable bypass capacitance coupled to an associated shared power distribution network, the at least one switchable bypass capacitance and at least one of the plurality of amplification paths responsive to a control signal configured to selectively ground the at least one switchable bypass capacitance and selectively enable the at least one of the amplification paths based on a selected operating mode.

Abstract: A device includes at least one first amplifier circuit configurable to receive and amplify an input radio frequency (RF) signal having a first carrier at a first input signal level and provide a first amplified RF signal, and at least one second amplifier circuit configurable to receive and amplify the input RF signal having a second carrier at a second input signal level and provide a second amplified RF signal, the at least one first amplifier circuit having a first input impedance, the at least one second amplifier circuit having a second input impedance.

Abstract: A device includes a first and a second low noise amplifier (LNA), a first degenerative inductance coupled between the first LNA and ground by a first ground connection, and a second degenerative inductance coupled between the second LNA and ground by a second ground connection, the first and second degenerative inductances configured to establish negative inductive coupling between the first and second degenerative inductances.

Abstract: A device includes a first and a second low noise amplifier (LNA), a first degenerative inductance coupled between the first LNA and ground by a first ground connection, and a second degenerative inductance coupled between the second LNA and ground by a second ground connection, the first and second degenerative inductances configured to establish negative inductive coupling between the first and second degenerative inductances.

Abstract: A device includes a first amplifier circuit coupled to a first transformer and a second transformer, the first transformer selectively coupled to a first shared power distribution network through a first switch, the second transformer selectively coupled to a second shared power distribution network through a second switch.

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract: Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device.

Abstract: Provided is an apparatus for generating remote plasma, which can improve thin-film quality by preventing an arc at a bias electrode. The apparatus includes a radio frequency (RF) electrode installed inside an upper portion of a chamber, a bias electrode installed apart from the RF electrode, and including a plurality of through holes through which plasma passes, wherein a bias power is supplied to the bias electrode, a plasma generating unit formed between the RF electrode and the bias electrode, wherein a plasma gas is supplied to the plasma generating unit, and a ground electrode installed under and spaced apart from the bias electrode, and including plasma through holes corresponding to the through holes of the bias electrode, wherein a pulsed DC bias of a second voltage level, which has a first voltage level periodically, is applied to the bias electrode.

Abstract: A method and apparatus controls power consumption of stations having a hierarchical structure when the stations transmit and receive a wireless signal to and from one another on a CSMA/CA wireless LAN. The controlling involves extracting information on frame transmission speed and transmission period information on first and second layers of the hierarchical structure from the wireless signal; determining a power-controlled period for each of the first and second layers based on the extracted information; and reducing the power consumption of the first and second layers by switching a current mode of the first and second layers to a predetermined mode for the power-controlled period if a reception address included in the extracted information is not identical to an address of the station.

Abstract: Disclosed is a method and an apparatus for self-calibrating direct current (DC) offset and imbalance between orthogonal signals, which may occur in a mobile transceiver. In the apparatus, a transmitter of a mobile terminal functions as a signal generator, and a receiver of the mobile terminal functions as a response characteristic detector. Further, a baseband processor applies test signals to the transmitter, receives the test signals returning from the receiver, and compensates the imbalance and DC offset for the transmitter side and the receiver side by using the test signals.

Abstract: Provided is an apparatus for generating remote plasma, which can improve thin-film quality by preventing an arc at a bias electrode. The apparatus includes a radio frequency (RF) electrode installed inside an upper portion of a chamber, a bias electrode installed apart from the RF electrode, and including a plurality of through holes through which plasma passes, wherein a bias power is supplied to the bias electrode, a plasma generating unit formed between the RF electrode and the bias electrode, wherein a plasma gas is supplied to the plasma generating unit, and a ground electrode installed under and spaced apart from the bias electrode, and including plasma through holes corresponding to the through holes of the bias electrode, wherein a pulsed DC bias of a second voltage level, which has a first voltage level periodically, is applied to the bias electrode.

Abstract: An apparatus for generating an in-phase/quadrature-phase (I/Q) signal in a wireless transceiver is disclosed, including a local oscillator for generating an oscillation signal, and first and second mixers for mixing an oscillation signal with a transmission/reception signal to convert the transmission/reception signal into a baseband or high-frequency signal. The apparatus includes a phase locked circuit for controlling the local oscillator, and a polyphase filter installed between the local oscillator and the mixers, for separating the oscillation signal from the local oscillator into an I signal and a Q signal depending on a control signal from the phase locked circuit, and outputting the separated I and Q signals to the first and second mixers, respectively.

Abstract: Provided is a mixer for use in a direct conversion receiver. The mixer includes Field Effect Transistors (FETs), a current source (IBias), two load resistors (RLoad), another FET, and two inductors L1 and L2. The FET M21 constitutes a current bleeding circuitry and the other components except for the two inductors L1 and L2 constitute a so-called Gilbert cell mixer.