Abstract: An image sensor and a method for manufacturing the same are provided. In the method, a photoresist is formed on a substrate including a photodiode region and a gate electrode opposite to the photodiode region on the basis of the gate electrode. An oxide layer is formed to a specific thickness on both the photodiode region and a part of the gate electrode. The photoresist is removed from the substrate and cleaned. A first oxide film is formed on the substrate, the gate electrode, and the oxide layer remaining on the photodiode region. A nitride film is formed on the first oxide film. And a second oxide film is formed on the nitride film. Blank etching is performed on the first oxide film, the nitride film, and the second oxide film to form a spacer at the side of the gate electrode.

Abstract: Provided is a method for manufacturing an image sensor. The method includes the following. A color filter layer is formed on a semiconductor substrate having a photodiode and a transistor formed thereon. A planarization layer is formed on the color filter layer. An LTO (Low Temperature Oxide) layer is formed on the planarization layer. A photoresist pattern is formed to correspond to the color filter layer on the LTO layer, and a reflow process is performed. A microlens array is formed by reactive ion etching the photoresist pattern and the LTO layer. A second reflow process may be performed on the photoresist pattern and/or the LTO layer during the reactive ion etching process.

Abstract: Embodiments relate to a CMOS image sensor and to a method for manufacturing a CMOS image sensor that may disperse stray beam between microlenses. According to embodiments, the method for manufacturing the CMOS image may include forming an interlayer dielectric layer on a semiconductor substrate including a plurality of photo diodes, forming a color filter layer corresponding to the photo diodes on the interlayer dielectric layer, forming a planarization layer on the color filter layer, forming microlenses on the planarization layer, after depositing an insulating layer over the microlenses, forming a trench in a concave lens shape in the insulating layer between the microlenses, and forming a concave lens gap-filling insulating materials inside the trench. In embodiments, concave lenses may be formed between microlenses in a CMOS image sensor and stray beams between the microlenses may be dispersed and recondensed into the microlenses.

Abstract: Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide layer, a nitride layer, and a second oxide layer may be formed over the substrate including the gate electrode. A photoresist pattern may be formed over the substrate to open the photodiode area centering on the gate electrode. A transformed nitride layer may be formed by selectively carrying out nitridation on the second oxide layer formed over the photodiode area centering on the gate electrode using the photoresist pattern as a mask. The photoresist mask pattern may be removed. A spacer may be formed over one side of the gate electrode by carrying out blank etch on the first oxide layer, the nitride layer, the transformed nitride layer, and the second oxide layer.

Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.

Abstract: A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole may be etched simultaneously.

Abstract: The present invention relates to a washing machine and a method of controlling the same. The washing machine includes a home network switch unit for selectively inputting a home network mode or a standby power mode, a standby power unit for supplying or shutting off a main power according to an operating state, and a microcomputer for controlling the standby power unit according to a mode set by the home network switch unit. Thus, the home network mode or the standby power mode is selected, if appropriate, through manipulation of a switch. Accordingly, the washing machine can be driven even when it is connected to a home network. When the standby power mode is selected, applied main power is shut off. Accordingly, there is an advantage in that a washing machine with minimized power consumption can be provided.

Abstract: An image sensor according to an embodiment can comprise a metal line layer formed on a semiconductor substrate including a light receiving device; a first microlens formed on the metal line layer; a color filter array formed on the first microlens; and a second microlens formed on the color filter array. An oxide layer pattern can be disposed between the metal line layer and the first microlens. A blocking layer can be arranged in the oxide layer pattern in regions between adjacent first microlenses.

Abstract: A method for manufacturing a semiconductor device capable of eliminating additional processes for forming an alignment key, thereby shortening the manufacturing process and lowering the manufacturing costs.

Abstract: A method of fabricating a metal line of a semiconductor device that prevents formation of serrations in a metal line to thereby increase operational reliability of a semiconductor device. The method includes forming a lower metal line in a semiconductor substrate; and then forming a first nitride layer as an etching stop layer over the semiconductor substrate including the lower metal line; and then forming a first insulating layer over the first nitride layer; and then forming a second nitride layer over the first insulating layer; and then forming a contact hole partially exposing the uppermost surface of the lower metal line by performing a first etching process; and then simultaneously forming a second insulating layer over the second nitride layer and a void in the contact hole; and then forming a trench corresponding spatially to the contact hole and partially exposing the uppermost surface of the lower metal line by performing a second etching process.

Abstract: Disclosed herein is a method of forming an inductor in a semiconductor device, the method including forming an etching-prevention film, a first interlayer insulating film, and a first hard mask film over a silicon semiconductor substrate in this sequence; selectively etching the first hard mask film to form a hole; forming a second interlayer insulating film over the first hard mask film; forming a second hard mask film over the second interlayer insulating film; forming a photoresist pattern having a trench forming opening over the second hard mask film; removing a part of the second hard mask film and a part of the second interlayer insulating film by using the photoresist pattern as an etching mask, to form a first trench in the second interlayer insulating film; removing the photoresist pattern and polymers produced in the first trench by ashing and cleaning process; etching the second interlayer insulating film by using the second hard mask film as an etching mask until the first hard mask film is expose

Abstract: Embodiments relate to a CMOS image sensor and to a method for manufacturing a CMOS image sensor that may disperse stray beam between microlenses. According to embodiments, the method for manufacturing the CMOS image may include forming an interlayer dielectric layer on a semiconductor substrate including a plurality of photo diodes, forming a color filter layer corresponding to the photo diodes on the interlayer dielectric layer, forming a planarization layer on the color filter layer, forming microlenses on the planarization layer after depositing an insulating layer over the microlenses, forming a trench in a concave lens shape in the insulating layer between the microlenses, and forming a concave lens gap-filling insulating materials inside the trench. In embodiments, concave lenses may be formed between microlenses in a CMOS image sensor and stray beams between the microlenses may be dispersed and recondensed into the microlenses.

Abstract: Provided is a method for fabricating an image sensor. In the method, a low temperature oxide layer is formed on a color filter layer, and a photoresist pattern is formed on the low temperature oxide layer. Subsequently, a heat treatment is performed on the photoresist pattern to form sacrificial microlenses. The sacrificial microlenses and the low temperature oxide layer are etched to form preliminary microlenses formed the low temperature oxide layer. The preliminary microlenses are etched to form microlenses having a reduced curvature radius in comparison with that of the preliminary microlenses.

Abstract: Provided is a method for manufacturing an image sensor. The method includes the following. A color filter layer is formed on a semiconductor substrate having a photodiode and a transistor formed thereon. A planarization layer is formed on the color filter layer. An LTO (Low Temperature Oxide) layer is formed on the planarization layer. A photoresist pattern is formed to correspond to the color filter layer on the LTO layer, and a reflow process is performed. A microlens array is formed by reactive ion etching the photoresist pattern and the LTO layer. A second reflow process may be performed on the photoresist pattern and/or the LTO layer during the reactive ion etching process.

Abstract: A method for manufacturing a semiconductor device that reduces the overall number of masking processes while also preventing short-circuiting between electrodes. The method can include sequentially forming a first insulating film, a lower metal layer, a second insulating material, an upper metal layer, and a third insulating material over a semiconductor substrate; forming a third insulating film and an upper electrode by performing a first etching process using a mask to pattern the third insulating material and the upper metal layer; and then forming a second insulating film and a lower electrode by performing a second etching process using the mask to pattern the second insulating material and the lower metal layer.

Abstract: A flash memory device fabricating method can include forming a plurality of gate patterns over a semiconductor substrate, forming a first spacer over the semiconductor substrate and against sidewalls of each gate pattern and a second spacer over the first spacer, forming an impurity region in the semiconductor substrate and between respective gate patterns, removing the second spacer, and then forming a pre-metal dielectric film over the semiconductor substrate including the gate patterns and the first spacer. The second space can be removed in order to expand a space between the gate patterns to thereby prevent generation of voids between the gate patterns.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a lower metal wiring formed over a semiconductor substrate. A first metal barrier layer can be formed over the lower metal wiring and an interlayer insulating layer formed over the first metal barrier layer. An upper metal wiring can be formed over the interlayer insulating layer. A contact may be formed for electrically connecting the lower metal wiring and the upper metal wiring. A second metal barrier layer pattern having a plurality of holes can be formed over the upper metal wiring and over the interlayer insulating layer. The dielectric constant of the interlayer insulating layer may be further reduced by forming an air gap between the interlayer insulating layer and the second metal barrier layer pattern including the plurality of holes.

Abstract: Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide layer, a nitride layer, and a second oxide layer may be formed over the substrate including the gate electrode. A photoresist pattern may be formed over the substrate to open the photodiode area centering on the gate electrode. A transformed nitride layer may be formed by selectively carrying out nitridation on the second oxide layer formed over the photodiode area centering on the gate electrode using the photoresist pattern as a mask. The photoresist mask pattern may be removed. A spacer may be formed over one side of the gate electrode by carrying out blank etch on the first oxide layer, the nitride layer, the transformed nitride layer, and the second oxide layer.

Abstract: Disclosed herein a method of manufacturing a semiconductor device, the method including: forming a plurality of layers over a semiconductor substrate having a lower structure including a transistor; forming a photoresist layer over the plurality of layers and patterning the photoresist layer in a contact hole shape; and etching the plurality of layers through a predetermined etching method using the patterned photoresist layer as an etching mask to form a contact hole.

Abstract: A semiconductor device and methods of fabricating the same are provided. The semiconductor device can include a tunnel oxide layer on a semiconductor substrate, a floating gate having a top surface with concave-convex shapes on the tunnel oxide layer, an ONO (oxide/nitride/oxide) layer on the floating gate, and a control gate on the ONO layer.