Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.

Abstract: A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole may be etched simultaneously.

Abstract: A method of forming a contact hole of a semiconductor device, the method comprising: forming a gate line and a source/drain region in a substrate; depositing an etch stopper layer on the substrate; depositing a first interlayer dielectric layer on the etch stopper layer and flattening the first interlayer dielectric layer exposing a portion of the etch stopper layer; removing the exposed portion of the etch stopper layer; forming a gate protective layer on the gate line; depositing a second interlayer dielectric layer on the substrate; and etching the second interlayer dielectric layer to form a first contact hole on the gate line and etching the second interlayer dielectric layer, the first interlayer dielectric layer, and the etch stopper layer to form a second contact hole on the source/drain region, wherein the gate protective layer protects the gate line during the formation of the first and second contact holes.

Abstract: A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate, a via exposing the substrate, a plug filling the via, a metal wiring layer on the first interlayer insulating film contacting the plug, and a second interlayer insulating film supported by the metal wiring and being partially suspended over the first interlayer insulating film, thereby forming an air gap. The second interlayer insulating film is provided with an aperture portion through which the first interlayer insulating film is exposed.