Abstract: A semiconductor memory device includes a mammy cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device, The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.

Abstract: The present invention relates to a novel method for preparing (S)—N1-(2-aminoethyl)-3-(4-alkoxyphenyl)propane-1,2-diamine trihydrochloride.

Abstract: The present specification relates to a novel hetero-cyclic compound, and an organic light emitting device using the same.

Abstract: The present invention relates to a novel method for preparing (S)—N1-(2-aminoethyl)-3-(4-alkoxyphenyl)propane-1,2-diamine trihydrochloride.

Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.

Abstract: A variable intake system includes a pair of surge tanks connected in a communicating manner to a main intake pipe through a low speed communication pipe and a high speed communication pipe, a middle speed communication pipe for connecting the pair of surge tanks, and a noise reducing member integrally provided at the middle speed communication pipe to reduce noise.

Abstract: A memory device includes a first data buffer receiving data of a first frequency band or a second frequency band, a first clock buffer providing a clock signal of the first frequency band to the first data buffer when the first data buffer receives the data of the first frequency band and providing a clock signal of the second frequency band to the first data buffer when the first data buffer receives the data of the second frequency band, a second data buffer receiving the data of the first frequency band or the second frequency band and receiving the clock signal of the second frequency band from the first clock buffer in response to receiving the data of the second frequency band, and a second clock buffer providing the clock signal of the first frequency band to the second data buffer in a first frequency band operation.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of bank arrays and a control logic circuit. The control logic circuit controls access to the memory cell array in response to a command and an address. A first number of memory cells are coupled to a bit-line of a first bank array of the plurality of bank arrays, a second number of memory cells are coupled to a bit-line of a second bank array of the plurality of bank arrays and the first number is different from the second number.

Abstract: A memory device includes a first data buffer receiving data of a first frequency band or a second frequency band, a first clock buffer providing a clock signal of the first frequency band to the first data buffer when the first data buffer receives the data of the first frequency band and providing a clock signal of the second frequency band to the first data buffer when the first data buffer receives the data of the second frequency band, a second data buffer receiving the data of the first frequency band or the second frequency band and receiving the clock signal of the second frequency band from the first clock buffer in response to receiving the data of the second frequency band, and a second clock buffer providing the clock signal of the first frequency band to the second data buffer in a first frequency band operation.

Abstract: A semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal.

Abstract: A semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of bank arrays and a control logic circuit. The control logic circuit controls access to the memory cell array in response to a command and an address. A first number of memory cells are coupled to a bit-line of a first bank array of the plurality of bank arrays, a second number of memory cells are coupled to a bit-line of a second bank array of the plurality of bank arrays and the first number is different from the second number.

Abstract: The present specification relates to a novel hetero-cyclic compound, and an organic light emitting device using the same.

Abstract: Disclosed are a bone conduction speaker module and bone conduction earphones having the bone conduction speaker modules. More particularly, the present invention relates to a bone conduction speaker module and bone conduction earphones having the bone conduction speaker modules, wherein the bone conduction speaker modules can accurately output sound, can stably output sound with fewer vibrations, enable a wearer to comfortably use the earphones, can prevent strain to the wearer by minimizing influence of magnetic force, can facilitate wearing of the earphones, and can prevent an accident from occurring by allowing the wearer to hear external sounds. To this end, a bone conduction speaker module used in earphones, headphones, and a hearing aid, includes: a housing including a first casing covering a portion coming into contact with a human body and a second casing covering a side of the first casing; a magnet part; and a voice coil part.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract: A variable intake system includes a pair of surge tanks connected in a communicating manner to a main intake pipe through a low speed communication pipe and a high speed communication pipe, a middle speed communication pipe for connecting the pair of surge tanks, and a noise reducing member integrally provided at the middle speed communication pipe to reduce noise.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract: A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

Abstract: An intake system of an engine may include an intake line supplying an engine with air, an exhaust line that exhaust gas combusted in the cylinder is exhausted, a housing disposed on the intake line and a compressor is disposed therein, the compressor is operated by a turbine disposed on an exhaust line, a recirculation line that recirculates the air from the intake line of a downstream side of the compressor to the intake line of an upstream side of the compressor, and an anti surge valve disposed on the recirculation line to open/close the recirculation line, wherein a length of a first section (l) that is straight from the anti surge valve is longer than two times the outlet diameter (d) of the anti surge valve in the recirculation line that is formed from the anti surge valve to an upstream side of the compressor.