Abstract: A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins.

Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

Abstract: A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

Abstract: A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins.

Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract: A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.