Abstract: A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

Abstract: A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternatively in correspondence with the first and second openings.

Abstract: A substrate bonding apparatus for a liquid crystal display device panel includes an upper chamber plate, a lower chamber plate opposing the upper chamber plate, an upper low vacuum chamber provided on the upper chamber plate, a lower low vacuum chamber provided on a rear surface of the lower chamber plate, a sealing member provided on the lower chamber plate, the sealing member projecting from a top surface of the lower chamber plate at a predetermined height to contact the upper chamber plate to form a high vacuum chamber therein, at least two holes provided in each of the upper and lower chamber plates, at least two flow shut-off systems shutting off each of the holes, vacuum pumping system for reducing pressures of the upper and lower low vacuum chambers to low vacuum states, and reducing the high vacuum chamber to a high vacuum state, and upper and lower stages provided to upper and lower chamber plates, respectively, within an inside space of the high vacuum chamber to affix first and second substrates o

Abstract: A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternately in correspondence with the first and second openings.

Abstract: A temperature detection circuit and method are provided. The temperature detection circuit samples a first delay time for an input signal at a target temperature to be detected, stores a first addresses generated as the sampled result, samples a second delay time for the input address at a present operating temperature, compares a second addresses generated as the sampled result with the first addresses, and generates a detection signal if the target temperature to be detected is the same as the present operating temperature. The temperature detection method is performed by the temperature detection circuit.

Abstract: A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternately in correspondence with the first and second openings.

Abstract: In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

Abstract: In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

Abstract: A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternately in correspondence with the first and second openings.

Abstract: An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode.

Abstract: Integrated circuits and methods use a margin test voltage generator that is powered at a first power supply voltage to generate a second power supply voltage that has a magnitude that is less than the magnitude of the first power supply voltage. During a low supply voltage margin test, a first logic circuit is powered at the first power supply voltage while a second logic circuit, which is the subject of the test, is powered at the second power supply voltage. As a result, the first power supply voltage may remain at a sufficient magnitude to reliably power other devices or components that are not undergoing the low supply voltage margin test.

Abstract: A row address circuit of a semiconductor memory device includes a signal generator that generates a pulse in an enable signal for an output circuit that provides a decoded address. The pulse has a first edge that is delayed relative to a corresponding first edge of a refresh count signal and a second edge that precedes a corresponding second edge of the count signal. Accordingly, the enable signal prevents changes in the output signal that could otherwise result from input of an external address during a refresh operation. Therefore, the present invention can prevent an invalid address by cutting off a predecoder before a transition of a refresh count signal to prohibit a change of a predecoded output.

Abstract: A device and method for generating non-false interrupt signals are disclosed. They discriminate between noise and real signals from the interrupt sources. The device includes: plural signal generators for supplying indiscriminate interrupt demanding signals in response to signals from plural interrupt sources, respectively; plural counters for counting the indiscriminate interrupt demanding signals from the signal generators, respectively, to produce count values; plural comparators for comparing reference values against the counts to produce authenticated interrupt demanding signals, respectively; and a priority determining unit for receiving the authenticated interrupt demanding signals, for determining the relative priorities of these signals, and for issuing interrupt signals according to the priorities.

Abstract: A device and method for generating an interrupt for a microcontroller (MCU) are disclosed.