Patents by Inventor Sang Thanh Nguyen
Sang Thanh Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7663921Abstract: Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.Type: GrantFiled: November 7, 2008Date of Patent: February 16, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
-
Patent number: 7661041Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: December 10, 2007Date of Patent: February 9, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
-
Publication number: 20100001765Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.Type: ApplicationFiled: June 28, 2009Publication date: January 7, 2010Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
-
Publication number: 20090323415Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: ApplicationFiled: July 22, 2009Publication date: December 31, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
-
Patent number: 7631231Abstract: In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.Type: GrantFiled: April 19, 2006Date of Patent: December 8, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Sang Thanh Nguyen, Hieu Van Tran, Hung O. Nguyen, Phil Klotzkin
-
Patent number: 7626863Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: February 16, 2007Date of Patent: December 1, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
-
Patent number: 7616028Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.Type: GrantFiled: November 19, 2007Date of Patent: November 10, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
-
Flash memory array having control/decode circuitry for disabling top gates of defective memory cells
Patent number: 7567458Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: September 26, 2005Date of Patent: July 28, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu -
Publication number: 20090160411Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: ApplicationFiled: December 19, 2008Publication date: June 25, 2009Applicant: SILICON STORAGE TECHNOLOGY, INC.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung O. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
-
Publication number: 20090067239Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: ApplicationFiled: November 7, 2008Publication date: March 12, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
-
Publication number: 20090067235Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: ApplicationFiled: December 10, 2007Publication date: March 12, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
-
Publication number: 20090052248Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: ApplicationFiled: August 28, 2008Publication date: February 26, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
-
Publication number: 20080290931Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.Type: ApplicationFiled: May 23, 2007Publication date: November 27, 2008Applicant: SILICON STORAGE TECHNOLOGY, INC.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly
-
Patent number: 7447073Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: February 16, 2007Date of Patent: November 4, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
-
Patent number: 7436258Abstract: A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.Type: GrantFiled: July 30, 2007Date of Patent: October 14, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin
-
Publication number: 20080239834Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.Type: ApplicationFiled: November 19, 2007Publication date: October 2, 2008Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
-
Publication number: 20080111532Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: ApplicationFiled: November 18, 2007Publication date: May 15, 2008Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van TRAN, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
-
Patent number: 7362084Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: GrantFiled: March 14, 2005Date of Patent: April 22, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
-
Patent number: 7345512Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.Type: GrantFiled: May 4, 2004Date of Patent: March 18, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
-
Patent number: 7325177Abstract: A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: November 17, 2004Date of Patent: January 29, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang