Abstract: An electric headrest sliding device includes a slider configured to be movable upwards and downwards by driving of a motor, a front frame of a headrest, and a rotation link configured to connect the slider to the front frame, wherein the rotation link is rotated forwards or rearwards to push or pull the front frame during upward-and-downward movement of the slider, thereby accurately adjusting the front and rear positions of the headrest.

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a capacitor disposed on the substrate and spaced apart from the first semiconductor chip in a first direction; an insulating layer disposed on the substrate and covering the capacitor; a first heat conductive layer at least partially surrounding side walls of the first semiconductor chip and disposed on the insulating layer, wherein the first heat conductive layer is in contact with the side walls of the first semiconductor chip, and wherein the first heat conductive layer includes a first material that is a conductive material; and a second heat conductive layer disposed on the first heat conductive layer, wherein the second heat conductive layer is in contact with the first heat conductive layer, wherein the second heat conductive layer includes a second material that is a non-conductive material.

Abstract: The present disclosure is to provide a biomarker-searching method that can predict responses to ICI treatment and overall survival of ICI-treated patients. When the device and the method according to the present disclosure are used, it is possible to detect a biomarker capable of accurately predicting effectiveness of ICI treatment on cancer patients and overall survival of the cancer patients. Accordingly, it is possible to maximize the effectiveness of ICI treatment.

Abstract: A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.

Abstract: An image sensor package according to an embodiment includes: an image sensor chip having a sensing area of a central part and an outer area surrounding the sensing area; a transparent substrate spaced apart from and above the image sensor chip and covering the image sensor chip; a bonding structure disposed between the image sensor chip and the transparent substrate and provided on an upper surface of the outer area; and a package substrate on which the image sensor chip is mounted and electrically connected to the image sensor chip, wherein the image sensor chip, on a plane, includes a photo absorption layer enclosing the edge of the sensing area and having a pattern protruded toward the bonding structure along a circumference.

Abstract: In the present disclosure, the present inventors validated the effectiveness of the co-essentiality network, constructed from the gene essentiality profile across cancer cells, as a robust platform for identifying anticancer targets. Furthermore, the co-essentiality network facilitated the drug repurposing not previously addressed by conventional molecular networks. These findings underline the value of co-essentiality networks in advancing precision oncology, offering new potential therapeutic avenues.

Abstract: A method for determining a substrate model for describing a first measurement dataset and a second measurement dataset relating to a performance parameter. The method include obtaining candidate basis functions for a plurality of substrate models. Steps 1 to 4 are performed iteratively for the first measurement dataset and the second measurement dataset until at least one stopping criterion is met so as to determine the substrate model, the steps including: 1. selecting a candidate basis function from the candidate basis functions; 2. updating a substrate model by adding the candidate basis function into this substrate model to obtain an updated substrate model; 3. evaluating the updated substrate model based on the first measurement dataset and/or second measurement dataset; and 4. determining whether to include the basis function within the substrate model based on the evaluation.

Abstract: According to the present disclosure, it is possible to predict a success or a failure of a clinical trial by reflecting the effect of a drug on a cell population and a human gene. Therefore, it is possible to solve the problems caused by excessive clinical trials, such as excessive use of the drug.

Abstract: A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having a first opening and a second opening that penetrate the connection substrate, a semiconductor chip on the first redistribution substrate and in the first opening of the connection substrate, a chip module on the first redistribution substrate and in the second opening of the connection substrate, and a molding layer that covers the semiconductor chip, the chip module, and the connection substrate. The chip module includes an inner substrate and a first passive device on the inner substrate. In the second opening, the molding layer covers the first passive device on the inner substrate.

Abstract: A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.

Abstract: A semiconductor package includes: a package substrate; a semiconductor chip disposed on the package substrate; a transparent substrate disposed on the semiconductor chip; and an adhesive layer that is disposed between the semiconductor chip and the transparent substrate. The adhesive layer is configured to block light. The transparent substrate includes: a first lower side that faces the semiconductor chip, a second lower side that faces the semiconductor chip and that is disposed above the first lower side, and a first inner side wall that connects the first lower side and the second lower side, and the adhesive layer is in contact with the second lower side and the first inner side wall.

Abstract: A bioelectronic device for regulating stem cell differentiation, a method for differentiating stem cells using the same, and a method for manufacturing the bioelectronic device. According to the present invention, it is possible to effectively control the differentiation of stem cells at a single-cell level, and to simultaneously perform a free radical inhibition function.

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a capacitor disposed on the substrate and spaced apart from the first semiconductor chip in a first direction; an insulating layer disposed on the substrate and covering the capacitor; a first heat conductive layer at least partially surrounding side walls of the first semiconductor chip and disposed on the insulating layer, wherein the first heat conductive layer is in contact with the side walls of the first semiconductor chip, and wherein the first heat conductive layer includes a first material that is a conductive material; and a second heat conductive layer disposed on the first heat conductive layer, wherein the second heat conductive layer is in contact with the first heat conductive layer, wherein the second heat conductive layer includes a second material that is a non-conductive material.

Abstract: A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.

Abstract: A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having a first opening and a second opening that penetrate the connection substrate, a semiconductor chip on the first redistribution substrate and in the first opening of the connection substrate, a chip module on the first redistribution substrate and in the second opening of the connection substrate, and a molding layer that covers the semiconductor chip, the chip module, and the connection substrate. The chip module includes an inner substrate and a first passive device on the inner substrate. In the second opening, the molding layer covers the first passive device on the inner substrate.

Abstract: A method for determining lithographic matching performance includes obtaining first monitoring data from recurrent monitoring for stability control for an available EUV scanner. For a DUV scanner, second monitoring data is similarly obtained from recurrent monitoring for stability control. The EUV first monitoring data are in a first layout. The DUV second monitoring data are in a second layout. A cross-platform overlay matching performance between the first lithographic apparatus and the second lithographic apparatus is determined based on the first monitoring data and the second monitoring data. This is done by reconstructing the first and/or second monitoring data into a common layout to allow comparison of the first and second monitoring data.

Abstract: The present invention relates to a method and system for an emergency rescue request and loss prevention. The method includes checking an operation mode activation signal by the electronic device connected to a portable device through Bluetooth low energy (BLE) communication, activating a loss prevention mode and outputting an alarm when the operation mode activation signal that a strength of a BLE signal transmitted from the portable device is a threshold value or less and transmitting to a pre-stored contact number a message which is generated on the basis of surroundings data acquired from at least one of a camera and a microphone provided in the electronic device, activating an emergency rescue request mode when the operation mode activation signal is generated from an outside of the portable device. The method and system can also be applied to other embodiments.

Abstract: A method of producing carbon nanotubes in a fluidized bed reactor includes preparing a carbon nanotube by supplying a catalyst and a carbon source to an interior of the fluidized bed reactor having an internal pressure of 0.5 barg to 1.2 barg (gauge pressure), thereby improving the yield and purity of carbon nanotubes.

Abstract: A workstation includes a receiver configured to receive identification information of an X-ray detector from the X-ray detector; a controller configured to set assign indicator information of the X-ray detector, based on the received identification information of the X-ray detector; an output unit configured to display the set assign indicator information of the X-ray detector; and a transmitter configured to transmit the set assign indicator information of the X-ray detector to the X-ray detector. The X-ray detector includes a transmitter configured to transmit the identification information of the X-ray detector to the workstation; a receiver configured to receive the assign indicator information from the workstation after the transmitter transmits the identification information of the X-ray detector to the workstation; and an output unit configured to display an assign indicator based on the received assign indicator information.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip.