Patents by Inventor Sang-Wan Nam

Sang-Wan Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515325
    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Patent number: 11495541
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Patent number: 11373716
    Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 28, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wandong Kim, Jinwoo Park, Seongjin Kim, Sang-wan Nam
  • Patent number: 11367493
    Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wandong Kim, Jinwoo Park, Seongjin Kim, Sang-Wan Nam
  • Patent number: 11322205
    Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Won Park, Sang-Wan Nam, Ji Yeon Shin, Won Bo Shim, Jung-Yun Yun, Ji Ho Cho, Sang Gi Hong
  • Publication number: 20220130467
    Abstract: An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.
    Type: Application
    Filed: July 15, 2021
    Publication date: April 28, 2022
    Inventors: JAE-DUK YU, SANG-WAN NAM, JONGHOON PARK, HO-JUN LEE
  • Publication number: 20220068397
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: WON-TAECK JUNG, SANG-WAN NAM, JINWOO PARK, JAEYONG JEONG
  • Publication number: 20220059168
    Abstract: A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 24, 2022
    Inventors: JUN-HO SEO, YONG-LAE KIM, HANEOL JANG, HYUKJE KWON, SANG-WAN NAM
  • Patent number: 11238934
    Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region. The peripheral circuit region includes a block selecting circuit, a block unselecting circuit, and a first metal pad. The memory cell region is vertically connected to the peripheral circuit region, and includes a first memory block and a second metal pad directly connected to the first metal pad. The block selecting circuit is connected with ground selection lines, word lines, and string selection lines, and provides corresponding driving voltages to the ground selection lines, the word lines, and the string selection lines in response to a block selection signal corresponding to the first memory block, respectively. The block unselecting circuit is connected only with specific string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Euihyun Cheon, Byungjun Min
  • Patent number: 11222697
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 11200952
    Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: December 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Won Park, Sang-Wan Nam, Ji Yeon Shin, Won Bo Shim, Jung-Yun Yun, Ji Ho Cho, Sang Gi Hong
  • Patent number: 11200955
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, Sang-Wan Nam, Jinwoo Park, Jaeyong Jeong
  • Patent number: 11170856
    Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
  • Patent number: 11164637
    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 2, 2021
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 11074978
    Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Patent number: 11056194
    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 6, 2021
    Inventors: Won-Bo Shim, Sang-Wan Nam, Ji-Ho Cho
  • Publication number: 20210117321
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Publication number: 20210118512
    Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: SANG WAN NAM, YONG HYUK CHOI, JUN YONG PARK, JUNG NO IM
  • Patent number: 10964398
    Abstract: A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
  • Patent number: RE48930
    Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kitae Park