Patents by Inventor Sang-Wan Nam

Sang-Wan Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250124983
    Abstract: A memory device includes an array of nonvolatile memory cells and a wordline voltage generator configured to drive: a selected word line within the array with a program voltage, a word line extending immediately adjacent the selected word line with a first voltage during the program operation, and an unselected word line within the array with a second voltage having a magnitude less than a magnitude of the first voltage, during a memory cell program operation.
    Type: Application
    Filed: April 17, 2024
    Publication date: April 17, 2025
    Inventors: Kwanghoe Heo, Seongjin Kim, Sang-Wan Nam
  • Publication number: 20250087256
    Abstract: Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells, and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit including a first pump block, a second pump block, and a common pump block. The voltage generating circuit connects the first pump block and the common pump block in parallel to generate a first operating voltage among the plurality of operating voltages and connects the common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages. The common pump block is configurable to match the first pump block, the second pump block, or both, as needed.
    Type: Application
    Filed: January 19, 2024
    Publication date: March 13, 2025
    Inventors: Yoonjae Lee, Yeji Shin, Sang-Wan Nam, Sang-Won Shim
  • Publication number: 20250036299
    Abstract: A memory package includes a printed circuit board, a first memory device that is stacked on the printed circuit board, and a second memory device stacked on the first memory device. The first memory device includes a first one-time programmable (OTP) block, the second memory device includes a second OTP block different from the first OTP block, and a horizontal distance from one side of the first memory device to the first OTP block is different from a horizontal distance from one side of the second memory device to the second OTP block.
    Type: Application
    Filed: August 6, 2024
    Publication date: January 30, 2025
    Inventors: JAE-HOON CHOI, SANG-WAN NAM, SANGYONG YOON, KOOKHYUN CHO
  • Patent number: 12176046
    Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n?1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n?1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 24, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yohan Lee, Sang-Wan Nam, Sang-Won Park, Jiho Cho, Eunhyang Park
  • Patent number: 12153812
    Abstract: A memory package includes a printed circuit board, a first memory device that is stacked on the printed circuit board, and a second memory device stacked on the first memory device. The first memory device includes a first one-time programmable (OTP) block, the second memory device includes a second OTP block different from the first OTP block, and a horizontal distance from one side of the first memory device to the first OTP block is different from a horizontal distance from one side of the second memory device to the second OTP block.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: November 26, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Hoon Choi, Sang-Wan Nam, Sangyong Yoon, Kookhyun Cho
  • Patent number: 12147340
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: November 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Patent number: 12125544
    Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 22, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: You-Se Kim, Sang-Wan Nam, Kee Ho Jung
  • Patent number: 12119063
    Abstract: Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: October 15, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Hyunggon Kim, Bong-Kil Jung, Younho Hong, Juseong Hwang
  • Patent number: 12094540
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: September 17, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, Sang-Wan Nam, Jinwoo Park, Jaeyong Jeong
  • Patent number: 12080358
    Abstract: A nonvolatile memory device including a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: September 3, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Kil Jung, Sang-Wan Nam, Jong Min Baek, Min Ki Jeon, Woo Chul Jung, Yoon-Hee Choi
  • Publication number: 20240161816
    Abstract: A memory device may include a reference voltage generator that generates a reference voltage, a voltage regulator that includes a plurality of driving blocks generating an internal voltage based on the reference voltage, and a power line that receives the internal voltage. At least one of the plurality of driving blocks may include a first unit driver that generates a first output current flowing through the power line based on the reference voltage and a change in the internal voltage, and a second unit driver that generates a second output current larger than the first output current flowing through the power line, based on the reference voltage and the change in the internal voltage. The first unit driver may generate the first output current faster than the second output current of the second unit driver.
    Type: Application
    Filed: October 6, 2023
    Publication date: May 16, 2024
    Inventors: SEONGJIN KIM, SANG-WAN NAM, Sungho MOON
  • Patent number: 11854982
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Publication number: 20230273880
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Patent number: 11715525
    Abstract: A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 1, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Ho Seo, Yong-Lae Kim, Haneol Jang, Hyukje Kwon, Sang-Wan Nam
  • Publication number: 20230221870
    Abstract: Disclosed is a nonvolatile memory device including a memory cell array including memory cells, bit lines and word lines connected with the memory cells, a common source line connected with the memory cells, a control logic circuit including a common source line noise control logic circuit and configured to generate voltages including a first voltage and a second voltage, a voltage selector configured to receive the voltages and configured to select at least one of the voltages, and a common source line driver configured to receive the at least one selected voltage and configured to control a voltage of the common source line, and the common source line noise control logic circuit is configured to control the voltage selector based on program information so as to select the at least one of the voltages.
    Type: Application
    Filed: October 10, 2022
    Publication date: July 13, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Euihyun CHEON, Sang-Wan NAM
  • Patent number: 11681616
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 20, 2023
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Publication number: 20230178154
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 8, 2023
    Inventors: WON-TAECK JUNG, SANG-WAN NAM, JINWOO PARK, JAEYONG JEONG
  • Publication number: 20230153000
    Abstract: A memory package includes a printed circuit board, a first memory device that is stacked on the printed circuit board, and a second memory device stacked on the first memory device. The first memory device includes a first one-time programmable (OTP) block, the second memory device includes a second OTP block different from the first OTP block, and a horizontal distance from one side of the first memory device to the first OTP block is different from a horizontal distance from one side of the second memory device to the second OTP block.
    Type: Application
    Filed: November 3, 2022
    Publication date: May 18, 2023
    Inventors: JAE-HOON CHOI, Sang-Wan Nam, Sangyong Yoon, Kookhyun Cho
  • Patent number: RE50306
    Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied. The present disclosure provides a memory device for detecting a word line bridge defect through erase verification of the memory device.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: February 18, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
  • Patent number: RE50325
    Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kitae Park