Patents by Inventor Sang-Wan Nam

Sang-Wan Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200372956
    Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region. The peripheral circuit region includes a block selecting circuit, a block unselecting circuit, and a first metal pad. The memory cell region is vertically connected to the peripheral circuit region, and includes a first memory block and a second metal pad directly connected to the first metal pad. The block selecting circuit is connected with ground selection lines, word lines, and string selection lines, and provides corresponding driving voltages to the ground selection lines, the word lines, and the string selection lines in response to a block selection signal corresponding to the first memory block, respectively. The block unselecting circuit is connected only with specific string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: SANG-WAN NAM, EUIHYUN CHEON, BYUNGJUN MIN
  • Publication number: 20200365211
    Abstract: A memory device comprises: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a first memory cell in the memory cell region, and a second memory cell different from the first memory cell in the memory cell region, wherein the first memory cell and the second memory cell are included in a same memory block as each other, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region, different from the first word line, connected to the second memory cell, an address decoder in the peripheral circuit region configured to apply one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines, and a control logic in the peripheral circuit region configured to control an erasing operation on the memory block, using the address decoder, wherein
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: SANG WAN NAM, YONG HYUK CHOI, JUN YONG PARK, JUNG NO IM
  • Patent number: 10839910
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 10825532
    Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Bo Shim, Sang-Wan Nam, Ji-Ho Cho
  • Patent number: 10804293
    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Sang-Wan Nam, Bong-Soon Lim
  • Patent number: 10803947
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Publication number: 20200312381
    Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Application
    Filed: October 1, 2019
    Publication date: October 1, 2020
    Inventors: SANG-WAN NAM, EUIHYUN CHEON, BYUNGJUN MIN
  • Publication number: 20200294601
    Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Dong Hun KWAK, Sang Wan NAM, Chi Weon YOON
  • Patent number: 10777233
    Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Euihyun Cheon, Byungjun Min
  • Patent number: 10770148
    Abstract: An operation method of a nonvolatile memory device includes applying a program voltage to a selected word line and programming a selected memory cell connected to the selected word line; reading an adjacent memory cell connected to an adjacent word line of the selected word line; and verifying the selected memory cell by adjusting charge sharing between the selected memory cell and a sensing node, which is connected to the selected memory cell through a bit line.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, So-Yeong Gwak, Sang-Wan Nam
  • Patent number: 10748621
    Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Publication number: 20200243144
    Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Won-Bo Shim, Sang-Wan Nam, Ji-Ho Cho
  • Publication number: 20200242030
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Patent number: 10726931
    Abstract: A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks. The method including detecting an invalid block among the plurality of memory blocks; determining an invalid pattern based on a state of the invalid block; and performing an operation on the invalid block such that the invalid block has the invalid pattern.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Raeyoung Lee, Hyunjung Kim, Sung-Bok Lee, Soyeong Gwak, Sang-wan Nam
  • Publication number: 20200194069
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: SANG-WAN NAM, WON-TAECK JUNG
  • Publication number: 20200185038
    Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 10679702
    Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Patent number: 10680013
    Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wan Nam, Won-bo Shim, Ji-ho Cho
  • Patent number: 10671529
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Publication number: 20200168547
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Application
    Filed: October 4, 2019
    Publication date: May 28, 2020
    Inventors: BONGSOON LIM, SANG-WAN NAM, SANG-WON PARK, SANG-WON SHIM, HONGSOO JEON, YONGHYUK CHOI