Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.

Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

Abstract: A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.

Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

Abstract: A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks. The method including detecting an invalid block among the plurality of memory blocks; determining an invalid pattern based on a state of the invalid block; and performing an operation on the invalid block such that the invalid block has the invalid pattern.

Abstract: An operation method of a nonvolatile memory device includes applying a program voltage to a selected word line and programming a selected memory cell connected to the selected word line; reading an adjacent memory cell connected to an adjacent word line of the selected word line; and verifying the selected memory cell by adjusting charge sharing between the selected memory cell and a sensing node, which is connected to the selected memory cell through a bit line.

Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.

Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.

Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

Abstract: A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) a pre-program of sequentially selecting a plurality of memory blocks and increasing threshold voltages of string selection transistors or ground selection transistors of the selected memory block and (2) after the pre-program is completed, a main program of sequentially selecting the plurality of memory blocks, programming string selection transistors or ground selection transistors of the selected memory block, and performing a verification by using a verification voltage.

Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells.

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

Abstract: Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.