Patents by Inventor Sang-Won Shim

Sang-Won Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193680
    Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Bong-soon LIM, Jin-young KIM, Sang-won SHIM, Il-han PARK
  • Patent number: 11043274
    Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
  • Patent number: 11011208
    Abstract: A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Hojoon Kim, Sang-won Park, Sang-won Shim, Wonbo Shim
  • Patent number: 10978481
    Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong-soon Lim, Jin-young Kim, Sang-won Shim, Il-han Park
  • Publication number: 20210065806
    Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
    Type: Application
    Filed: July 22, 2020
    Publication date: March 4, 2021
    Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
  • Publication number: 20210065805
    Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
    Type: Application
    Filed: April 17, 2020
    Publication date: March 4, 2021
    Inventors: Yonghyuk CHOI, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
  • Publication number: 20210036015
    Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell army, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the
    Type: Application
    Filed: October 19, 2020
    Publication date: February 4, 2021
    Inventors: Bong-soon LIM, Jin-young KIM, Sang-won SHIM, Il-han PARK
  • Publication number: 20210005629
    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: BONGSOON LIM, SANG-WAN NAM, SANG-WON PARK, SANG-WON SHIM, HONGSOO JEON, YONGHYUK CHOI
  • Publication number: 20200312379
    Abstract: A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.
    Type: Application
    Filed: October 2, 2019
    Publication date: October 1, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Hojoon Kim, Sang-won Park, Sang-won Shim, Wonbo Shim
  • Publication number: 20200258911
    Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Bong-soon LIM, Jin-young KIM, Sang-won SHIM, Il-han PARK
  • Publication number: 20200230647
    Abstract: Disclosed are a method and an apparatus for converting a musical element so as to provide a vibration in an electronic device. According to various embodiments of the present invention, an electronic device may comprise: a display; a vibration generation apparatus for generating a vibration; and a processor functionally connected to the display and the vibration generation apparatus, wherein the processor is configured to: select multiple frequencies, using a musical element; set at least one vibration on the basis of the selected multiple frequencies; and generate a vibration pattern on the basis of the set vibration. Various elements are possible.
    Type: Application
    Filed: February 22, 2018
    Publication date: July 23, 2020
    Inventors: Sang-Won SHIM, Yonggu LEE, Joongsam YUN, Minkoo KANG
  • Patent number: 10699782
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Dongkyo Shim, Kitae Park, Sang-Won Shim
  • Patent number: 10672791
    Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong-soon Lim, Jin-young Kim, Sang-won Shim, Il-han Park
  • Publication number: 20200168547
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Application
    Filed: October 4, 2019
    Publication date: May 28, 2020
    Inventors: BONGSOON LIM, SANG-WAN NAM, SANG-WON PARK, SANG-WON SHIM, HONGSOO JEON, YONGHYUK CHOI
  • Publication number: 20200065029
    Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.
    Type: Application
    Filed: April 25, 2019
    Publication date: February 27, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Taehyun Kim, Chankyung Kim, Sang-won Shim, Suk-Soo Pyo
  • Publication number: 20190325952
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: SANG-WON PARK, DONGKYO SHIM, KITAE PARK, SANG-WON SHIM
  • Patent number: 10410728
    Abstract: A nonvolatile memory device for reducing hot-carrier injection (HCI) and a programming method of the nonvolatile memory device, the programming method of the nonvolatile memory device includes programming memory cells included in a cell string in a direction from an upper memory cell adjacent to a string selection transistor to a lower memory cell adjacent to a ground selection transistor from among a plurality of memory cells; when a selected memory cell is programmed, applying a first inhibition voltage to first non-selected word lines connected to first non-selected memory cells located over the selected memory cell; and applying a second inhibition voltage to second non-selected word lines connected to second non-selected memory cells located under the selected memory cell when a predetermined delay time elapses after the first inhibition voltage is applied.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Won Shim
  • Patent number: 10388367
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Dongkyo Shim, Kitae Park, Sang-Won Shim
  • Publication number: 20190164991
    Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 30, 2019
    Inventors: Bong-soon LIM, Jin-Young KIM, Sang-Won SHIM, Il-han PARK
  • Publication number: 20190139968
    Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.
    Type: Application
    Filed: July 16, 2018
    Publication date: May 9, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-won SHIM, Bong-soon LIM