Abstract: A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

Abstract: A nonvolatile memory device may include a cell array, a first page buffer, and a second page buffer. The first page buffer may be connected to a first memory cell of the cell array and may store first sensing data generated by sensing whether a program operation of the first memory cell is completed during a program verify operation. The second page buffer may be connected to a second memory cell of the cell array. During the program verify operation, the second page buffer may generate and store first verify data based on second sensing data generated by sensing whether a program operation of the second memory cell is completed, may receive the first sensing data from the first page buffer, and may store second verify data generated by accumulating the first sensing data and the first verify data.

Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

Abstract: An electronic device includes a display, a speaker, a vibrator, a memory for storing information and instructions for execution, and a processor coupled to the display, the speaker, the vibrator, and the memory, wherein the processor is configured to provide a notification associated with the information stored in the memory. The processor is configured to obtain a current value of the information, to compare the current value with a target value of the information, and to provide a notification of a first type via the display, the speaker or the vibrator when the current value is within a range of the target value and is not equal to the target value.

Abstract: A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

Abstract: A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.

Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.

Abstract: A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings. The vertical nonvolatile memory device is configured to apply the non-selection read voltage to at least one unselected word line of the cell string a desired time period after the applying of the non-selection read voltage to the at least one selection line.

Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.

Abstract: A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

Abstract: A nonvolatile memory device including memory blocks, a pre-decoder, and a row decoder is disclosed. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.

Abstract: A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings. The vertical nonvolatile memory device is configured to apply the non-selection read voltage to at least one unselected word line of the cell string a desired time period after the applying of the non-selection read voltage to the at least one selection line.

Abstract: According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.

Abstract: Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

Abstract: According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.