Abstract: A key input device combined with a key display unit and a digital appliance having the same are disclosed. The key input device includes a key display unit for displaying a character or an image that identifies a key, a touch sensing unit that moves down and up by a pressure applied to this key, and a signal generation unit for generating an electric signal in accordance with the pressure applied to the key, wherein the character or the image displayed on the key display unit can be changed.

Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

Abstract: A bismuth yttrium titanate (BYT) film having the composition of formula (I) has enhanced residual polarization and electric fatigue properties with excellent ferroelectric property, and therefore, it can be advantageously used in an electric or electronic device including a FRAM device: Bi4-xYxTi3O12??(I) wherein x is an integer of 0.1 to 2.

Abstract: An EEPROM includes a tunneling opening having an inclined or a stepped sidewall. A tunnel insulation layer is formed within the tunneling opening. Using a flowed photoresist pattern as an etching mask, the gate insulator is etched to form a tunneling opening having an inclined sidewall. Thus, the tunnel insulation layer can be formed in a smaller area than an area defined by a photolithography. As a result, a width of an active region and a width of a wordline are decreased to reduce a unit cell size.

Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Abstract: A key input device combined with a key display unit and a digital appliance having the same are disclosed. The key input device includes a key display unit for displaying a character or an image that identifies a key, a touch sensing unit that moves down and up by a pressure applied to this key, and a signal generation unit for generating an electric signal in accordance with the pressure applied to the key, wherein the character or the image displayed on the key display unit can be changed.

Abstract: A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.

Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

Abstract: A lanthanum complex of formula (I) having a low evaporation temperature can be used as a useful precursor for MOCVD of a BLT thin layer on semiconductor devices. wherein A is pentamethyldiethylenetriamine(PMDT) or triethoxytriethyleneamine(TETEA).

Abstract: The present invention relates to an organometal complex and a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method for preparing a metal silicate thin layer using same. The inventive method can easily prepare the metal silicate thin layer having a desired composition which can be effectively used as a gate insulating layer for various semiconductor devices.

Abstract: A method of fabricating an exposure mask including the steps of forming a chrome layer, a first photo resist, an Ag layer as a conductive layer and a second photo resist on a transparent quartz substrate, in sequence; forming and using a second photo resist pattern to form a conductive layer pattern by etching the conductive layer; removing the second photo resist pattern; forming an oxide layer for shielding light at the surface of the conductive layer pattern and exposing the first photo resist using the conductive layer pattern with the oxide layer thereon; forming a first photo resist pattern exposing the chrome layer and forming a mask pattern including the chrome layer by selectively etching the exposed chrome layer; and removing the conductive layer pattern including the oxide and the first photo resist pattern.

Abstract: A bismuth yttrium titanate (BYT) film having the composition of formula (I) has enhanced residual polarization and electric fatigue properties with excellent ferroelectric property, and therefore, it can be advantageously used in an electric or electronic device including a FRAM device:

Abstract: The present invention relates to an organometal complex and a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method for preparing a metal silicate thin layer using same. The inventive method can easily prepare the metal silicate thin layer having a desired composition which can be effectively used as a gate insulating layer for various semiconductor devices.

Abstract: A lanthanum complex of formula (I) having a low evaporation temperature can be used as a useful precursor for MOCVD of a BLT thin layer on semiconductor devices.

Abstract: A method of fabricating an exposure mask for semiconductor manufacture to improve the accuracy of critical dimensions of the mask pattern.

Abstract: A liquid organocuprous compound of formula (I) of the present invention can be conveniently used in a low-temperature CVD process for the production of a contaminant-free copper film having good step-coverage and hole-filling properties: ##STR1## wherein: R.sup.1 represents a C.sub.3-8 cycloalkyl group, andR.sup.2 and R.sup.3 are each independently a perfluorinated C.sub.1-4 alkyl group.