Abstract: Provided are a semiconductor device, and/or an electronic device and a memory device both including the semiconductor device. The semiconductor device includes a lower electrode, an upper electrode spaced apart from the lower electrode, a channel layer between the lower electrode and the upper electrode, a gate insulating layer in the channel layer, an insertion layer provided between the channel layer and the gate insulating layer, and a gate electrode on the gate insulating layer. The channel layer has a vertical channel structure extending in a vertical direction from the lower electrode toward the upper electrode. The insertion layer may include a nitride of a metal and/or an oxynitride of a metal, and the metal may include one or more of niobium (Nb), vanadium (V), or tantalum (Ta).

Abstract: Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.

Abstract: A ferroelectric field effect transistor includes a channel layer, a gate electrode facing the channel layer, a ferroelectric layer between the channel layer and the gate electrode, and a channel intermediate layer between the channel layer and the ferroelectric layer, wherein the channel layer and the channel intermediate layer each include an oxide semiconductor material, and a concentration of oxygen vacancies in the channel intermediate layer may be greater than a concentration of oxygen vacancies in the channel layer.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device of the disclosure may include a lower electrode, an upper electrode spaced apart from the lower electrode, a channel between the lower electrode and the upper electrode, a gate insulating layer provided in the channel, and a gate electrode provided in the gate insulating layer, wherein the channel may include a plurality of oxide semiconductor layers and at least one aluminum oxide layer, the plurality of oxide semiconductor layers being spaced apart from each other, and the at least one aluminum oxide layer being inserted between the plurality of oxide semiconductor layers.

Abstract: Provided are semiconductor devices and methods of manufacturing the semiconductor device. The semiconductor device includes a lower electrode, a channel on the lower electrode and including an oxide semiconductor, an upper electrode on the channel and including tungsten or molybdenum, a first interlayer between the lower electrode and the channel, and a second interlayer between the channel and the upper electrode, wherein the channel has a vertical channel structure extending in a vertical direction from the lower electrode to the upper electrode, and the first interlayer and the second interlayer include different materials.

Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.

Abstract: A semiconductor device includes an oxide semiconductor layer including an oxide semiconductor, a conductive layer, and a buffer layer disposed between the oxide semiconductor layer and the conductive layer, where the buffer layer includes graphene.

Abstract: A vertically stacked memory device includes a plurality of bit lines extending in a first direction, a plurality of oxide semiconductor layers including a plurality of oxide semiconductor layer sets each including one or more oxide semiconductor layers connected to a separate, respective bit line of the plurality of bit lines and extending in a second direction, the second direction intersecting with the first direction, a plurality of capacitors electrically connected to separate, respective oxide semiconductor layers of the plurality of oxide semiconductor layers, and a plurality of word lines extending to intersect with the plurality of oxide semiconductor layers in a third direction intersecting with both the first direction and the second direction, wherein each oxide semiconductor layer includes an oxide semiconductor material in which a proportion of tin (Sn) among all metals therein is about 50 at % or more to about 100 at % or less.

Abstract: A memory device includes a bit line extending in a first direction, an oxide semiconductor layer extending in a second direction intersecting the first direction and connected to the bit line, the oxide semiconductor layer comprising a source region, a drain region, and a channel region between the source region and the drain region, a capacitor electrically connected to the oxide semiconductor layer, a word line extending to intersect the oxide semiconductor layer in a third direction intersecting the first direction and the second direction, a first insulator on both side surfaces of the source region and the drain region in the third direction, and a second insulator different from the first insulator and on both sides of the channel region in the third direction.

Abstract: A method of controlling a user terminal, performed by a computer system that is a server or the user terminal, may include determining whether the user terminal is located within a customized region of a space based on a location of the user terminal, the customized region being associated with at least one service element, and in response that the user terminal is determined to be located in the customized region, controlling the user terminal based on the service element.

Abstract: Provided are a semiconductor thin film and a semiconductor device including the same. The semiconductor device includes an oxide semiconductor layer having an amorphous phase and including tin (Sn) and a metal element other than tin (Sn), wherein a content of tin (Sn) is greater than 50 at % of a total content of tin (Sn) and the metal element other than tin (Sn), a first electrode and a second electrode disposed on the oxide semiconductor layer and spaced apart from each other, a gate electrode spaced apart from the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode.

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

Abstract: A layout analysis method includes segmenting a layout pattern into a plurality of polygons in a shape of a rectangle, extracting a conversion characteristic value by applying tolerance to a characteristic value, the characteristic value comprising shape information of each of the plurality of polygons, extracting a total hash value of each of the plurality of polygons by using the conversion characteristic value of each of the plurality of polygons, grouping patterns of the plurality of polygons into a plurality of groups based on the total hash value of each of the plurality of polygons, and extracting a unique pattern from each of the groups.

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

Abstract: Provided is a method for providing augmented content, wherein whether a user terminal is located in a preset unit space is determined on the basis of the location of the user terminal, and if the user terminal is determined to be located in the unit space, an image captured by a camera is displayed through an augmented reality (AR) view by being augmented with content associated with the unit space.

Abstract: A position recognition method and a system based on visual information processing are disclosed A position recognition method according to one embodiment including the steps of: generating a frame image through a camera; transmitting, to a server, a first global pose of the camera and the generated frame image; and receiving, from the server, a second global pose of the camera estimated on the basis of a pose of an object included in the transmitted frame image.

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a layout and forming a photoresist pattern on a substrate using a photomask that is manufactured with the layout corrected by the OPC operation. The OPC operation includes sectioning the layout into a low-level patch and a high-level patch, performing a first OPC operation on the low-level patch, the first OPC operation including generating a first boundary correction pattern of a curvilinear shape on a boundary between the low-level patch and the high-level patch, performing a second OPC operation on the high-level patch, the second OPC operation including a second boundary correction pattern of a curvilinear shape on the boundary, and conforming the first boundary correction pattern and the second boundary correction pattern to each other to generate a conformed boundary correction pattern of a curvilinear shape.