Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

Abstract: A pouch forming apparatus according to an embodiment of the present disclosure includes a die unit in which a forming groove is formed in a portion where a pouch film is disposed, a partition plate that divides the forming groove into at least two, and a pressing unit that presses the pouch film disposed on the die unit to form an electrode assembly-receiving part, wherein a chamfer part is formed at the lower end of the partition plate.

Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.

Abstract: Embodiments disclosed herein include methods, systems and/or devices configured to generate historical parameters of a sigmoidal rate expression based on the sigmoidal rate expression and measured data of a battery. The embodiments may further be configured to predict future parameters of the sigmoidal rate expression based on the sigmoidal rate expression and the historical parameters. The embodiments may further be configured to predict an aging state of the battery based on the sigmoidal rate expression and the future parameters. Additional embodiments are directed to methods, systems, and/or devices configured to synthesize training data based on measured battery data, a sigmoidal rate expression, and ranges for parameters of the sigmoidal rate expression. The additional embodiments may further be configured to train a machine-learning model using the synthesized training data.

Abstract: Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include at least one layer of silicon-containing material and at least one layer of silicon-and-germanium-containing material along the substrate. The methods may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor within the processing region. The methods may include contacting the at least one layer of silicon-containing material and the at least one layer of silicon-and-germanium-containing material with plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor.

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

Abstract: A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

Abstract: A neuromorphic apparatus includes a three-dimensionally-stacked synaptic structure, and includes a plurality of unit synaptic modules, each of the plurality of unit synaptic modules including a plurality of synaptic layers, each of the plurality of synaptic layers including a plurality of stacked layers, and each of the plurality of unit synaptic modules further including a first decoder interposed between two among the plurality of synaptic layers. The neuromorphic apparatus further includes a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit synaptic modules to be accessed, and a third decoder that generates an address of one among a plurality of memristers to be accessed in a memrister array of one among the plurality of synaptic layers included in the one among the plurality of unit synaptic modules to be accessed.

Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.

Abstract: Provided is a method of fabricating a semiconductor device using a curvilinear OPC method. The method of fabricating the semiconductor device includes performing an optical proximity correction (OPC) step on a layout to generate a correction pattern, the correction pattern having a curvilinear shape, performing a mask rule check (MRC) step on the correction pattern to generate mask data, and forming a photoresist pattern on a substrate using a photomask, which is manufactured based on the mask data. The MRC step includes generating a width skeleton in the correction pattern, generating a width contour, which satisfies a specification of a mask rule for a linewidth, from the width skeleton, and adding the correction pattern and the width contour to generate an adjusting pattern.

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

Abstract: A field-effect transistor includes a gate structure comprising a structure in which a first insulating layer, a first gate electrode, and a second insulating layer are sequentially stacked on a first conductive layer, the gate structure surrounding a first hole through the first insulating layer and exposing a part of the first conductive layer; a second conductive layer on the second insulating layer and surrounding a second hole connected to the first hole and exposing a part of the first conductive layer; a first gate insulating layer covering an inner wall of the gate structure exposed by the first hole; a semiconductor layer covering a part of the first conductive layer exposed through the first hole and the second hole, the first gate insulating layer, and the second conductive layer; a second gate insulating layer covering the semiconductor layer; and a second gate electrode filling the first and second holes.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: A neuromorphic apparatus includes a three-dimensionally-stacked synaptic structure, and includes a plurality of unit synaptic modules, each of the plurality of unit synaptic modules including a plurality of synaptic layers, each of the plurality of synaptic layers including a plurality of stacked layers, and each of the plurality of unit synaptic modules further including a first decoder interposed between two among the plurality of synaptic layers. The neuromorphic apparatus further includes a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit synaptic modules to be accessed, and a third decoder that generates an address of one among a plurality of memristers to be accessed in a memrister array of one among the plurality of synaptic layers included in the one among the plurality of unit synaptic modules to be accessed.

Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.