Patents by Inventor Sang-yong Kim
Sang-yong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220352389Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: ApplicationFiled: July 12, 2022Publication date: November 3, 2022Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
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Publication number: 20220254884Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.Type: ApplicationFiled: October 18, 2021Publication date: August 11, 2022Inventors: Jae-Jung KIM, Sang Yong KIM, Byoung Hoon LEE, Chan Hyeong LEE
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Patent number: 11411124Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: GrantFiled: December 28, 2020Date of Patent: August 9, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
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Publication number: 20210151610Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: ApplicationFiled: December 28, 2020Publication date: May 20, 2021Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
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Patent number: 10974805Abstract: A ballast water treatment apparatus equipped with devices for injecting bromine salt and ozone includes a ballast pipe, a ballast pump, a bromine salt injection part and an ozone processor, wherein the injection part includes a bromine salt storage tank; a bromine salt transfer pipe connected to the ballast pipe for injecting bromine salt supplied from the bromine salt storage tank into the ballast pipe; and a bromine salt injection pump in the transfer pipe for pressurizing bromine salt to be injected into the ballast pipe, and the ozone processor includes an ozone injection device for supplying ozone to the ballast pipe; a mixer in the ballast pipe for mixing ozone supplied from the ozone injection device and seawater transferred into the ballast pipe; and an ozone transfer pipe connected to the mixer of the ballast pipe for injecting ozone supplied from the ozone injection device into the ballast pipe.Type: GrantFiled: November 19, 2015Date of Patent: April 13, 2021Assignee: NK CO., LTD.Inventors: Sung Jin Park, Seung Je Yoon, Dong Yeon Cho, Sang Yong Kim, Tae Hyeon Park, In Dong Kim
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Patent number: 10923602Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: GrantFiled: August 6, 2019Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
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Publication number: 20210013207Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Jae Jung KIM, Young Suk CHAI, Sang Yong KIM, Hoon Joo NA, Sang Jin HYUN
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Patent number: 10847515Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: GrantFiled: November 29, 2018Date of Patent: November 24, 2020Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
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Patent number: 10600913Abstract: A semiconductor device and a method for fabricating the same are provided.Type: GrantFiled: August 10, 2018Date of Patent: March 24, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun Chung, Jong Ho Park, Seung Ha Oh, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
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Publication number: 20200035842Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: ApplicationFiled: August 6, 2019Publication date: January 30, 2020Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
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Patent number: 10381490Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: GrantFiled: July 20, 2018Date of Patent: August 13, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
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Patent number: 10332994Abstract: A semiconductor integrated circuit device may include an isolating layer, a buried gate, source and drain regions, a dielectric layer having a high dielectric constant and an insulating interlayer. The isolating layer may be formed on a semiconductor substrate to define an active region. The buried gate may be formed in the active region of the semiconductor substrate. The source and drain regions may be formed in the active region at both sides of the buried gate. The dielectric layer may be configured to surround the source and drain regions. The insulating interlayer may be formed on the dielectric layer.Type: GrantFiled: December 2, 2016Date of Patent: June 25, 2019Assignee: SK hynix Inc.Inventors: Dong Yean Oh, Sang Yong Kim
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Patent number: 10271908Abstract: An optical tracking system includes a reference marker part stationarily disposed relative to a first region; a sticker marker part attached in a sticker form to a second region capable of being rigidly registered with the first region; a shape measurement part measuring three-dimensional shapes of the first region and the second region; a tracking sensor part sensing the reference marker part and the shape measurement part; and a processing part acquiring a first coordinate transformation relationship among the reference marker part, the tracking sensor part, the shape measurement part, and the first region of the patent and a second coordinate transformation relationship among the reference marker part, the tracking sensor part, the shape measurement part, and the second region of the patient and tracking the first region by extracting a third coordinate transformation relationship between the first region and the second region.Type: GrantFiled: December 18, 2015Date of Patent: April 30, 2019Assignee: KOH YOUNG TECHNOLOGY INC.Inventor: Sang Yong Kim
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Publication number: 20190109135Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: ApplicationFiled: November 29, 2018Publication date: April 11, 2019Inventors: Jae Jung KIM, Young Suk CHAI, Sang Yong KIM, Hoon Joo NA, Sang Jin HYUN
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Publication number: 20190088798Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: ApplicationFiled: July 20, 2018Publication date: March 21, 2019Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
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Patent number: 10177149Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: GrantFiled: March 7, 2017Date of Patent: January 8, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
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Publication number: 20180350983Abstract: A semiconductor device and a method for fabricating the same are provided.Type: ApplicationFiled: August 10, 2018Publication date: December 6, 2018Inventors: Won Keun CHUNG, Jong Ho PARK, Seung Ha OH, Sang Yong KIM, Hoon Joo NA, Sang Jin HYUN
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Publication number: 20180263708Abstract: An optical tracking system includes a reference marker part stationarily disposed relative to a first region; a sticker marker part attached in a sticker form to a second region capable of being rigidly registered with the first region; a shape measurement part measuring three-dimensional shapes of the first region and the second region; a tracking sensor part sensing the reference marker part and the shape measurement part; and a processing part acquiring a first coordinate transformation relationship among the reference marker part, the tracking sensor part, the shape measurement part, and the first region of the patent and a second coordinate transformation relationship among the reference marker part, the tracking sensor part, the shape measurement part, and the second region of the patient and tracking the first region by extracting a third coordinate transformation relationship between the first region and the second region.Type: ApplicationFiled: December 18, 2015Publication date: September 20, 2018Inventor: Sang Yong KIM
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Patent number: 9994583Abstract: The present invention relates to a method for preparing a curable bicyclic compound derived from biomass. The method includes preparing starting materials furan and methyl acrylate by preparing furan from hemicellulose extracted from biomass, and methyl acrylate from glycerol generated from biomass, preparing an intermediate compound comprising a bicycle and an alcohol functional group by reacting the furan and the methyl acrylate through a Diels-Alder reaction and consecutive reduction, and preparing a curable bicyclic compound that includes the bicycle and an epoxide functional group by reacting the intermediate compound and epichlorohydrin.Type: GrantFiled: July 28, 2016Date of Patent: June 12, 2018Assignee: Korea Institute of Industrial TechnologyInventors: Jin-Ku Cho, Sang-Yong Kim, Do-Hoon Lee, Bo-Ra Kim, Baek-Jin Kim, Jae-Won Jung, Sang-Hyeup Lee, Jae-Soung Lee
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Publication number: 20180130905Abstract: A semiconductor device and a method for fabricating the same are provided.Type: ApplicationFiled: June 12, 2017Publication date: May 10, 2018Inventors: Won Keun CHUNG, Jong Ho PARK, Seung Ha OH, Sang Yong KIM, Hoon Joo NA, Sang Jin HYUN