Abstract: The present invention provides a pharmaceutical composition for nasal administration comprising mometasone furoate and azelastine hydrochloride, wherein the pharmaceutical composition comprises thaumatin as an agent for reducing bitterness and irritation.

Abstract: The present invention relates to an apparatus and method for assisting parking, the apparatus including: an image sensor photographing front/rear view images of a vehicle; and an estimated trace of vehicle generation and process unit generating an estimated trace of the vehicle to a parking target area using steering angle information of the vehicle, and overlaying the estimated trace of the vehicle to the photographed front/rear view images of the vehicle, wherein the estimated trace of the vehicle includes a first estimated trace of the vehicle based on a rear wheel of the vehicle and a second estimated trace of the vehicle based on a front wheel of the vehicle.

Abstract: A display apparatus and method for assisting parking is disclosed, the method comprising combining images of all directions of a vehicle photographed by a photographing unit installed on the vehicle into an around view, generating an expected travel trace of the vehicle using steering angle information of the vehicle, overlaying the expected travel trace of the vehicle on the around view, and displaying the overlaid around view along with the expected travel trace of the vehicle, wherein the expected travel trace includes a first expected travel trace made by rear wheels of the vehicle and a second expected travel trace made by front wheels of the vehicle.

Abstract: The present invention relates to a method for purifying an erythropoietin analog having a low isoelectric point below 4 by adding an N-linked sugar chain with high purity. In accordance with the present invention, the erythropoietin analog having an isoelectric point below 4, which is an isoform having more sialic acid residues, can be effectively purified via three-step chromatographic processes in short time at lower cost.

Abstract: An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity. When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized.

Abstract: Provided are a solar cell and a method of manufacturing the same. The method of manufacturing the solar cell includes stacking a solar cell device layer containing GaN on a sacrificial substrate, etching the solar cell device layer to expose the sacrificial substrate, thereby forming one or more solar cell devices comprising the solar cell device layer, anisotropically etching the exposed sacrificial substrate, contacting the solar cell devices to a stamping processor to remove the solar cell devices from the sacrificial substrate, and transferring the solar cell devices onto a receiving substrate. A high temperature semiconductor process may be performed on a substrate such as a silicon substrate to transfer the solar cell devices onto the substrate, thereby manufacturing flexible solar cells. Also, a large number of solar cells may be excellently aligned on a large area. In addition, economical solar cells may be manufactured.

Abstract: A double-sided cutting insert includes: rectangular shaped upper and lower surfaces formed at upper and lower sides of the insert; four side surfaces of each of the upper and lower surfaces; an assembling hole perpendicular to the upper surface; major cutting edges, at corners of one side surface, and rotationally symmetrical with respect to a center of an outer shape of the insert in a plan view where the upper surface is the front and rotationally symmetrical with respect to the center in a front view where the one of the side surfaces is the front; minor cutting edges, formed at one side of each major cutting edge, and rotationally symmetrical with respect to the center in the plan view; and minor side surfaces formed on a surface where the minor cutting edges meet the side surfaces and inclined toward the center with respect to an assembling hole central axis.

Abstract: The present invention relates to video encoding/decoding methods and device, wherein the video encoding method according to the invention comprises the following steps: acquiring information of peripheral blocks; setting the information about a current block based on the information of the peripheral blocks; and encoding the current block based on the set information, wherein the current block and the peripheral blocks may be a CU (coding unit).

Abstract: The present invention relates to an expression vector for animal cells, comprising: (a) CSP-B (Cytotoxic Serine Protease-B) 5?-SAR (Scaffold or Matrix Attachment Region); (b) a promoter operable in animal cells; and (c) a polyadenylation sequence, and to a method for producing recombinant proteins using same. The vector of the present invention includes CSP-B 5?-SAR, and thus has the effect of overcoming the inhibition of gene expression according to the position of a foreign gene introduced into an animal cell, and significantly improving the expression rate of a target protein. The vector of the present invention effectively expresses recombinant proteins for drugs or antibodies in animal cells. The vector of the present invention and the method for producing recombinant proteins using same may be very usefully applied to the industrial mass production of drugs.

Abstract: A method of manufacturing a flexible piezoelectric device including laminating a first metal layer on a silicon oxide layer on a silicon substrate. The method further includes laminating a device on the first metal layer and annealing the first metal layer to oxidize the first metal into a first metal oxide. The method further includes etching the first metal oxide to separate the device from the silicon oxide layer and transferring the separated device to a flexible substrate using a transfer layer. The metal oxide layer laminated on the silicon substrate is etched to separate the device from the substrate. As a result, physical damage of the silicon substrate is prevented and a cost of using expensive single-crystal silicon substrate is reduced.

Abstract: An embedded package that may be realized by surrounding a semiconductor chip (or a semiconductor die) in a package substrate. A semiconductor chip of an embedded package may be electrically connected to external connection terminals through interconnection wires instead of bumps, and the interconnection wires may be formed using a wire bonding process. A high reliability embedded package results.

Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.

Abstract: A cutting insert, and more particularly, an improved double-sided cutting insert is provided, which provides improved machinability obtained due to increased rake angle, without compromising coupling state. The double-sided cutting insert includes a top surface, a bottom surface, a plurality of lateral relief surfaces connecting the top and bottom surfaces, and a cutting edge formed by the top and bottom surfaces and the plurality of lateral relief surfaces, in which one or more lateral relief surfaces of the plurality of lateral relief surfaces are formed into three stages in sequence which are a first positive surface, a negative surface and a second positive surface in a direction from the top surface to the bottom surface.

Abstract: A method of manufacturing LED display is provided. The method provides a sacrificial substrate on which RGB LED device layers are formed, respectively. The method etches and patterns the LED device layer to manufacture RGB LED devices, respectively. The method removes the sacrificial substrate in a lower side of the LED device. The method contacts a stamping processor to the RGB LED devices to separate the RGB LED devices from the sacrificial substrate. The method transfers the LED device, which is attached to the stamping processor, to a receiving substrate.

Abstract: The present invention relates to a jig for processing the inner surface of an aluminum alloy Winston cone baffle having the thickness of a sheet through an ultra-precision machining, the jig having a shape identically corresponding to the outer shape of a Winston cone baffle having a can body shape made up of compound parabolic, and divided into an upper plate jig and a lower plate jig in formation, wherein the upper plate jig is divided in two, a left side jig and a right side jig, which are formed to correspond in shape and size so as to enable isolation or coupling to/from each other, and the inner surface of the Winston cone baffle attached inside the upper plate jig is made to enable ultra-precision machining at the cutting speed of 220 m/min-300 m/min, which enables the inner surface of the Winston cone baffle to process a slickenside having approximately 4 nm of surface roughness, and in particular, ultra-precision machining at surface roughness of Ra=2.

Abstract: The present invention provides a pharmaceutical composition for nasal administration comprising mometasone furoate and azelastine hydrochloride, wherein the pharmaceutical composition comprises thaumatin as an agent for reducing bitterness and irritation.

Abstract: A lateral insulated-gate bipolar transistor includes a buried insulation layer which opens only part of the collector ion implantation region and isolates the other regions, thereby reducing the loss by the turn-off time. The lateral insulated-gate bipolar transistor further includes a deep ion implantation region formed to face towards the open part of the collector ion implantation region, thereby decreasing the hole current injected into a base region under an emitter ion implantation region, and thereby greatly increasing the latch-up current level by relatively increasing the hole current injected into the deep ion implantation region having no latch-up effect.

Abstract: An apparatus for generating/decoding an animated image code, and a method thereof. The animated image code frame includes an image code frame which is divided into code cells expressing minimum unit data, and in which the minimum unit data is expressed in an area located inside the code cells and is formed by combining one or more color, gradation, and patterns; and a design layer which is formed by combining color or gradation used in the image code frame and color or gradation distinguishable on the basis of a threshold value, and which is displayed by overlapping the frame image. By utilizing changes in respective animated frames, an animated image code can be generated and decoded in which motion can be expressed by using a display medium.

Abstract: Provided is an optical system for a thermal image microscope. The optical system includes an image forming unit and a relay unit. The image forming unit forms a focus. The relay unit elongates an optical path. Here, the image forming unit includes six lenses. The relay unit includes two lenses. Aspherical surfaces of the lenses are all convex surfaces.

Abstract: A lateral insulated-gate bipolar transistor includes a buried insulation layer which opens only part of the collector ion implantation region and isolates the other regions, thereby reducing the loss by the turn-off time. The lateral insulated-gate bipolar transistor further includes a deep ion implantation region formed to face towards the open part of the collector ion implantation region, thereby decreasing the hole current injected into a base region under an emitter ion implantation region, and thereby greatly increasing the latch-up current level by relatively increasing the hole current injected into the deep ion implantation region having no latch-up effect.