Patents by Inventor Sang Cheon Park
Sang Cheon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120318Abstract: A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.Type: ApplicationFiled: May 4, 2023Publication date: April 11, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Don Mun, Sang Cheon Park
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Patent number: 11955449Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.Type: GrantFiled: November 10, 2022Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Jihwan Suh, Un-Byoung Kang, Taehun Kim, Hyuekjae Lee, Jihwan Hwang, Sang Cheon Park
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Patent number: 11955271Abstract: A radio frequency (RF) weak magnetic field detection sensor includes a ferromagnetic core, a pickup coil disposed to surround the ferromagnetic core, a substrate that includes an opening, a core pad connected to the ferromagnetic core and a coil pad connected to the pickup coil, and an insulating tube interposed between the ferromagnetic core and the pickup coil. The insulating tube includes a bobbin around which the pickup coil is wound, and a core hole formed to pass through the bobbin and configured to accommodate the ferromagnetic core.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Jang Yeol Kim, In Kui Cho, Hyunjoon Lee, Sang-Won Kim, Seong-Min Kim, Jung Ick Moon, Woo Cheon Park, Je Hoon Yun, Jaewoo Lee, Ho Jin Lee, Dong Won Jang, Kibeom Kim, Seungyoung Ahn
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Publication number: 20240105679Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.Type: ApplicationFiled: April 14, 2023Publication date: March 28, 2024Inventors: YOUNG KUN JEE, SANGHOON LEE, UN-BYOUNG KANG, SANG CHEON PARK, JUMYONG PARK, HYUNCHUL JUNG
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Patent number: 11916309Abstract: An apparatus and method for transmitting and receiving magnetic field signals in a magnetic field communication system are provided. The apparatus includes a controller configured to generate a communication signal, matching units that are configured to receive the communication signal and that respectively correspond to different matching frequencies, and loop antennas that are connected to the matching units, respectively, and that are configured to convert communication signals according to the different matching frequencies into magnetic transmission signals in the form of magnetic field energy and to transmit the magnetic transmission signals.Type: GrantFiled: December 15, 2020Date of Patent: February 27, 2024Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jaewoo Lee, In Kui Cho, Sang-Won Kim, Seong-Min Kim, Ho Jin Lee, Jang Yeol Kim, Jung Ick Moon, Woo Cheon Park, Je Hoon Yun, Hyunjoon Lee, Dong Won Jang
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Publication number: 20240030214Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.Type: ApplicationFiled: October 3, 2023Publication date: January 25, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon PARK, Dae-Woo Kim, Taehun Kim, Hyuekjae Lee
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Publication number: 20230395523Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Inventors: Sang Cheon PARK, Young Min LEE, Dae-Woo KIM, Hyuek Jae LEE
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Patent number: 11798929Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.Type: GrantFiled: July 21, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon Park, Dae-Woo Kim, Hyuekjae Lee, Taehun Kim
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Patent number: 11776916Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.Type: GrantFiled: March 12, 2021Date of Patent: October 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon Park, Young Min Lee, Dae-Woo Kim, Hyuek Jae Lee
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Patent number: 11694996Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.Type: GrantFiled: April 30, 2021Date of Patent: July 4, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuekjae Lee, Un-Byoung Kang, Sang Cheon Park, Jinkyeong Seol, Sanghoon Lee
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Publication number: 20230076511Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.Type: ApplicationFiled: November 10, 2022Publication date: March 9, 2023Inventors: Jihwan Suh, Un-Byoung Kang, Taehun Kim, Hyuekjae Lee, Jihwan Hwang, Sang Cheon Park
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Patent number: 11508685Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.Type: GrantFiled: August 13, 2020Date of Patent: November 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jihwan Suh, Un-Byoung Kang, Taehun Kim, Hyuekjae Lee, Jihwan Hwang, Sang Cheon Park
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Patent number: 11362905Abstract: Provided are a data receiving method and device to increase a probability of receiving normal data from a plurality of peripheral devices. A data receiving method of a device includes receiving current data from any one peripheral device of a plurality of peripheral devices, determining whether the received current data is normal data, calculating a probability that next data is normal data, on the basis of a result of the determination, and determining whether to receive the next data according to the calculated probability, in which the next data is data transmitted by the any one peripheral device or another peripheral device.Type: GrantFiled: May 7, 2019Date of Patent: June 14, 2022Assignee: AGENCY FOR DEFENSE DEVELOPMENTInventors: Sang Cheon Park, Eun Jeong Jeong, Seong Lyun Kim
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Publication number: 20220165722Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.Type: ApplicationFiled: July 21, 2021Publication date: May 26, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon PARK, Dae-Woo Kim, Taehun Kim, Hyuekjae Lee
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Publication number: 20220068829Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.Type: ApplicationFiled: March 12, 2021Publication date: March 3, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sang Cheon PARK, Young Min LEE, Dae-Woo KIM, Hyuek Jae LEE
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Publication number: 20220028834Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.Type: ApplicationFiled: April 30, 2021Publication date: January 27, 2022Inventors: HYUEKJAE LEE, UN-BYOUNG KANG, SANG CHEON PARK, JINKYEONG SEOL, SANGHOON LEE
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Publication number: 20210377127Abstract: Provided are a data receiving method and device to increase a probability of receiving normal data from a plurality of peripheral devices. A data receiving method of a device includes receiving current data from any one peripheral device of a plurality of peripheral devices, determining whether the received current data is normal data, calculating a probability that next data is normal data, on the basis of a result of the determination, and determining whether to receive the next data according to the calculated probability, in which the next data is data transmitted by the any one peripheral device or another peripheral device.Type: ApplicationFiled: May 7, 2019Publication date: December 2, 2021Inventors: Sang Cheon PARK, Eun Jeong JEONG, Seong Lyun KIM
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Patent number: 11097381Abstract: A filler wire may include a rod including an aluminum-silicon (Al—Si) alloy powder and a fluoride flux powder, and a sheath including zinc (Zn) alloy and surrounding the rod.Type: GrantFiled: June 17, 2019Date of Patent: August 24, 2021Assignees: Hyundai Motor Company, Kia Motors CorporationInventor: Sang-Cheon Park
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Publication number: 20210125955Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.Type: ApplicationFiled: August 13, 2020Publication date: April 29, 2021Inventors: JIHWAN SUH, UN-BYOUNG KANG, TAEHUN KIM, HYUEKJAE LEE, JIHWAN HWANG, SANG CHEON PARK
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Patent number: 10904766Abstract: Provided is a method of determining a node location in a cognitive radio network environment in which data is transmitted from a first node to a third node via a second node. The method includes information requesting wherein the first node transmits an information request signal to a plurality of second nodes in a preset segmented region; information receiving wherein the first node receives, from the second nodes, location information and frequency resource information for each second node corresponding to the transmitted information request signal; and segment determining wherein the first node determines one segment in the segmented region based on the received location information and frequency resource information.Type: GrantFiled: August 20, 2018Date of Patent: January 26, 2021Assignee: AGENCY FOR DEFENSE DEVELOPMENTInventors: Sang Cheon Park, Young Taek Hong, Jee Min Kim, Seong Lyun Kim