Abstract: A fuel cell system includes: an oxygen concentration module to produce oxygen-enriched air by separating nitrogen from air, and a first air supply line connected to the oxygen concentration module to supply air to the oxygen concentration module. The fuel cell system further includes: a heating unit provided in the first air supply line to selectively heat air by using waste heat discharged from an external heat source provided outside a fuel cell stack, a second air supply line connected to the oxygen concentration module and configured to supply air to the oxygen concentration module independently of the first air supply line, a cooling unit provided in the second air supply line and configured to selectively cool air by using outside cold energy, and a stack connection line which connects the oxygen concentration module and the fuel cell stack and supplies the oxygen-enriched air to the fuel cell stack.

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device may include a first interlayer insulating film containing therein a plurality of pores, a first line structure in the first interlayer insulating film, an inserted insulating film extending along and on a upper surface of the first interlayer insulating film and in contact with the first interlayer insulating film, a barrier insulating film in contact with the inserted insulating film and extending along an upper surface of the inserted insulating film and an upper surface of the first line structure, a second interlayer insulating film on the barrier insulating film and a second line structure disposed in the second interlayer insulating film and connected to the first line structure.

Abstract: A femtosecond laser source according to an embodiment of the present invention includes: a pulse generator that converts a continuous wave laser into an optical pulse train; a burst generator that separates the optical pulse train into a plurality of burst pulses; a pulse amplification and spectral broadening unit that expands the spectrum by amplifying a plurality of burst pulses; and a pulse compressor that compresses a plurality of amplified burst pulses to generate a femtosecond laser with a pulse width of 1 picosecond (10?12 s) or less.

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.

Abstract: Provided is a stack molding machine including an upper mold having formed therein a first runner and a first gate serving as a path of a resin material, a first intermediate plate provided under and combined with the upper mold, and having formed therein a first molding connected to the first gate to mold at least a portion on a first substrate placed under the first intermediate plate, a dummy plate provided under and spaced a certain distance apart from the first intermediate plate, a second intermediate plate provided under the dummy plate, and having formed therein a second molding connected to a second gate to mold at least a portion under a second substrate placed under the dummy plate, and a lower mold having formed therein a second runner and the second gate serving as a path of the resin material, and combined with the second intermediate plate.

Abstract: Provided is a method of fabricating a battery protection circuit package, the method including preparing a complex package substrate obtained by connecting a flexible printed circuit board (PCB) including at least one external connection terminal for connection to an external device, to a rigid PCB for mounting components thereon, mounting the complex package substrate on a lead frame including at least one metal tab for connection to a battery cell, and encapsulating at least portions of the complex package substrate and the lead frame with a molded part while exposing the at least one metal tab and the at least one external connection terminal.

Abstract: Provided is a method of fabricating a battery protection circuit package, the method including preparing a complex package substrate obtained by connecting a flexible printed circuit board (PCB) including at least one external connection terminal for connection to an external device, to a rigid PCB for mounting components thereon, mounting the complex package substrate on a lead frame including at least one metal tab for connection to a battery cell, and encapsulating at least portions of the complex package substrate and the lead frame with a molded part while exposing the at least one metal tab and the at least one external connection terminal.

Abstract: A method of fabricating a battery protection circuit package according to one aspect of the present invention includes forming a first mounting structure by mounting battery protection circuit elements on a printed circuit board (PCB), forming a second mounting structure by mounting the first mounting structure on a lead frame which comprises an input/output terminal portion for external connection and at least one metal tab for battery cell connection, forming an encapsulation structure by encapsulating the second mounting structure with a molding material to encapsulate at least a part of the battery protection circuit elements while exposing the input/output terminal portion and the at least one metal tab of the lead frame, and bonding at least one flexible printed circuit board (FPCB) to the input/output terminal portion of the encapsulation structure.

Abstract: Provided is a method of fabricating a battery protection circuit package, the method including preparing a complex package substrate obtained by connecting a flexible printed circuit board (PCB) including at least one external connection terminal for connection to an external device, to a rigid PCB for mounting components thereon, mounting the complex package substrate on a lead frame including at least one metal tab for connection to a battery cell, and encapsulating at least portions of the complex package substrate and the lead frame with a molded part while exposing the at least one metal tab and the at least one external connection terminal.

Abstract: A laser decontamination system according to an embodiment of the present invention includes: a laser generator generating a laser beam; an optical head inserted inside a pipe and focusing the laser beam on a contamination material inside the pipe for laser ablation; a first optical fiber connecting the laser generator and the optical head and transmitting the laser beam to the optical head; a spectroscope for analyzing a plasma spectrum generated in the pipe by the laser ablation; a second optical fiber connecting the spectroscope and the optical head and transmitting the plasma spectrum to the spectroscope; a dust collector for collecting a dust generated in the pipe by the laser ablation; a dust collection pipe connecting the dust collector and the inside of the pipe and transmitting the dust to the dust collector; and a blocking film positioned between the optical head and the pipe to block the dust.

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.