Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.

Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.

Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.

Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.

Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.

Abstract: A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes.

Abstract: The memory system includes at least one volatile memory configured to store data. The memory system also includes a non-volatile memory controller configured to provide a control signal to allow the data to be stored in a non-volatile memory during a power interruption mode. In addition, the memory system includes a termination resistor (TER) configured to control a data path in response to a power interruption signal.

Abstract: A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes.

Abstract: The memory system includes at least one volatile memory configured to store data. The memory system also includes a non-volatile memory controller configured to provide a control signal to allow the data to be stored in a non-volatile memory during a power interruption mode. In addition, the memory system includes a termination resistor (TER) configured to control a data path in response to a power interruption signal.

Abstract: The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of supplying and measuring an electric current through a pad. The semiconductor device includes a memory cell, a data pad configured to receive data to be programmed into the memory cell or a write current to be supplied to the memory cell from an external device, and output data read out from the memory cell or a cell current flowing from the memory cell to the external device, and a path switching unit configured to set up a path so that the memory cell and the data pad are directly coupled when a test operation is performed.

Abstract: A reference voltage generator generates a reference voltage having a stable voltage level insensitive to a temperature variation. A reference voltage generator includes a current generating unit configured to generate a reference current proportional to temperature increase, a voltage adjusting unit configured to adjust a reference voltage corresponding to a current level of the reference current, and a start-up driving unit configured to drive and amplify the reference voltage while the voltage adjusting unit operates.

Abstract: A nonvolatile semiconductor device and a method for testing the same are provided. The nonvolatile semiconductor device includes a current generating unit configured to generate a set write current depending on a step pulse that is generated based on a reference current and output the set write current to a memory cell, and a current measuring unit configured to measure a step duration of the step pulse and output a measured result outside of a chip during an activation period of a test enable signal.

Abstract: A write driver circuit includes a write control unit and a write driver. The write control unit is configured to generate a write control current according to data to be stored. The write driver is configured to generate a write current for writing the data into a memory cell, in response to the write control current and an address signal, wherein the write driver changes the magnitude of the write current according to the write control current and the address signal.

Abstract: The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of supplying and measuring an electric current through a pad. The semiconductor device includes a memory cell, a data pad configured to receive data to be programmed into the memory cell or a write current to be supplied to the memory cell from an external device, and output data read out from the memory cell or a cell current flowing from the memory cell to the external device, and a path switching unit configured to set up a path so that the memory cell and the data pad are directly coupled when a test operation is performed.