Patents by Inventor Sangram Alapati
Sangram Alapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10929184Abstract: An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.Type: GrantFiled: March 25, 2019Date of Patent: February 23, 2021Assignee: International Business Machines CorporationInventors: Sangram Alapati, Hima B. Nimmagadda, Satish K. Sadasivam
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Patent number: 10884749Abstract: Aspects of the present disclosure relate to control of speculative demand loads. In some embodiments, the method includes receiving instructions for a branch in a program, detecting the branch load is in the cache, monitoring a number of completed loads for the program, determining a cache pollution ratio of executed loads to completed loads, providing the cache pollution ratio to a branch prediction unit, and altering load instructions for the branch based on the cache pollution ratio.Type: GrantFiled: March 26, 2019Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Satish Kumar Sadasivam, Puneeth A. H. Bhat, Shruti Saxena, Sangram Alapati
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Publication number: 20200310813Abstract: Aspects of the present disclosure relate to control of speculative demand loads. In some embodiments, the method includes receiving instructions for a branch in a program, detecting the branch load is in the cache, monitoring a number of completed loads for the program, determining a cache pollution ratio of executed loads to completed loads, providing the cache pollution ratio to a branch prediction unit, and altering load instructions for the branch based on the cache pollution ratio.Type: ApplicationFiled: March 26, 2019Publication date: October 1, 2020Inventors: Satish Kumar Sadasivam, Puneeth A.H. Bhat, Shruti Saxena, Sangram Alapati
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Publication number: 20190220312Abstract: An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Sangram Alapati, Hima B. Nimmagadda, Satish K. Sadasivam
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Patent number: 10241834Abstract: An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.Type: GrantFiled: November 29, 2016Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Sangram Alapati, Hima B. Nimmagadda, Satish K. Sadasivam
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Publication number: 20180150333Abstract: An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: Sangram Alapati, Hima B. Nimmagadda, Satish K. Sadasivam
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Patent number: 9928068Abstract: A system may include a memory to store an enhancer to identify a branch instruction, having a miss-prediction rate above a threshold, in an executing thread. The system may additionally include an instruction update unit to modify an operation code (opcode) of the branch instruction, where a modified opcode of a branch instruction indicates an instruction fetch priority for an executing thread. The system may further include a processor, having an instruction decode unit to set a modified instruction fetch priority of the first executing thread based on the modified opcode of the branch instruction, and an instruction fetch unit to retrieve instructions for the first executing thread from the instruction cache at a first rate, the first rate indicated by the modified instruction fetch priority of the first executing thread.Type: GrantFiled: December 7, 2015Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Sangram Alapati, Puneeth A. Bhat, Satish K. Sadasivam
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Patent number: 9753776Abstract: A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.Type: GrantFiled: December 1, 2015Date of Patent: September 5, 2017Assignee: International Business Machines CorporationInventors: Sangram Alapati, Puneeth A. Bhat, Satish K. Sadasivam
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Publication number: 20170161076Abstract: A system may include a memory to store an enhancer to identify a branch instruction, having a miss-prediction rate above a threshold, in an executing thread. The system may additionally include an instruction update unit to modify an operation code (opcode) of the branch instruction, where a modified opcode of a branch instruction indicates an instruction fetch priority for an executing thread. The system may further include a processor, having an instruction decode unit to set a modified instruction fetch priority of the first executing thread based on the modified opcode of the branch instruction, and an instruction fetch unit to retrieve instructions for the first executing thread from the instruction cache at a first rate, the first rate indicated by the modified instruction fetch priority of the first executing thread.Type: ApplicationFiled: December 7, 2015Publication date: June 8, 2017Inventors: Sangram Alapati, Puneeth A. Bhat, Satish K. Sadasivam
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Publication number: 20170153922Abstract: A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.Type: ApplicationFiled: December 1, 2015Publication date: June 1, 2017Inventors: Sangram Alapati, Puneeth A. Bhat, Satish K. Sadasivam
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Patent number: 9158640Abstract: A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case.Type: GrantFiled: November 1, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 9129057Abstract: The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.Type: GrantFiled: May 1, 2012Date of Patent: September 8, 2015Assignee: International Business Machines CorporationInventors: Satish K. Sadasivam, Prathiba Kumar, Rajan Ravindran, Sangram Alapati
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Publication number: 20150127984Abstract: A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 9021281Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.Type: GrantFiled: November 12, 2013Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Sangram Alapati, Amit Dugar, Prathiba Kumar, Satish K. Sadasivam
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Patent number: 8930760Abstract: A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: GrantFiled: December 17, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 8914515Abstract: A system, and computer program product for cloud optimization using workload analysis are provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.Type: GrantFiled: October 28, 2011Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Gowri Shankar Palani, Rajan Ravindran, Satish Kumar Sadasivam
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Patent number: 8904208Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.Type: GrantFiled: November 4, 2011Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Amit Dugar, Prathiba Kumar, Satish K. Sadasivam
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Patent number: 8892949Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: GrantFiled: November 1, 2013Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 8850266Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: GrantFiled: June 14, 2011Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 8838801Abstract: A method for cloud optimization using workload analysis is provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.Type: GrantFiled: July 16, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Gowri Palani, Rajan Ravindran, Satish Kumar Sadasivam