Abstract: A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.

Abstract: A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.

Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Abstract: The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.

Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.

Abstract: A method for cloud optimization using workload analysis is provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.

Abstract: A method, system, and computer program product for cloud optimization using workload analysis are provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud competing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.

Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Abstract: A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to branch to a piggyback interrupt handler corresponding to a piggyback interrupt vector. Based upon the determination, the hypervisor either branches to the piggyback interrupt handler or to an administrating interrupt handler that corresponds to the administrating interrupt vector.

Abstract: A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.

Abstract: A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In response to copying the operating system interrupt handlers into the reserved space in the allocated block of memory, custom interrupt handlers from the kernel module are copied over the operating system interrupt handlers in the interrupt vector memory location. The custom interrupt handlers after being copied into the interrupt vector memory location handle all interrupts received by the operating system.

Abstract: A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to branch to a piggyback interrupt handler corresponding to a piggyback interrupt vector. Based upon the determination, the hypervisor either branches to the piggyback interrupt handler or to an administrating interrupt handler that corresponds to the administrating interrupt vector.

Abstract: According to one aspect of the present disclosure a method and technique for processor verification using an abstract test case is disclosed. The method comprises identifying a format for an abstract instruction of an abstract test case, selecting an instruction from an instruction pool corresponding to the identified format, and generating a real test case for processor verification by modifying the abstract instruction based on the instruction selected from the instruction pool.

Abstract: A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In response to copying the operating system interrupt handlers into the reserved space in the allocated block of memory, custom interrupt handlers from the kernel module are copied over the operating system interrupt handlers in the interrupt vector memory location. The custom interrupt handlers after being copied into the interrupt vector memory location handle all interrupts received by the operating system.