Patents by Inventor Sang-Uhn CHA

Sang-Uhn CHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921579
    Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Heung Kim, Jun Hyung Kim, Chang-Yong Lee, Sang Uhn Cha, Kyung-Soo Ha
  • Publication number: 20230185664
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 15, 2023
    Inventors: Hoi-Ju CHUNG, SANG-UHN CHA, HO-YOUNG SONG, HYUN-JOONG KIM
  • Patent number: 11593199
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Publication number: 20230012525
    Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.
    Type: Application
    Filed: March 11, 2022
    Publication date: January 19, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Heung KIM, Jun Hyung KIM, Chang-Yong LEE, Sang Uhn CHA, Kyung-Soo HA
  • Patent number: 11557332
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Patent number: 11438016
    Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu, Young-Sik Kim, Su-Yeon Doo
  • Patent number: 11385960
    Abstract: A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Uhn Cha
  • Publication number: 20220121518
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 11239960
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-ju Chung, Sang-Uhn Cha, Hyun-Joong Kim
  • Patent number: 11231996
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 11223373
    Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu, Young-Sik Kim, Su-Yeon Doo
  • Patent number: 11216339
    Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hun Seo, Kwang-Il Park, Seung-Jun Bae, Sang-Uhn Cha
  • Patent number: 11194657
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Kyung-Ryun Kim, Young-Hun Seo
  • Publication number: 20210272623
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
  • Patent number: 11031065
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Publication number: 20210149764
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Application
    Filed: December 30, 2020
    Publication date: May 20, 2021
    Inventors: HOI-JU CHUNG, SANG-UHN CHA, HO-YOUNG SONG, HYUN-JOONG KIM
  • Publication number: 20210091791
    Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Inventors: SANG-UHN CHA, YE-SIN RYU, YOUNG-SIK KIM, SU-YEON DOO
  • Publication number: 20210081278
    Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Inventors: Young-Hun SEO, Kwang-Il PARK, Seung-Jun BAE, Sang-Uhn CHA
  • Patent number: 10929225
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Publication number: 20210044393
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-ju CHUNG, Sang-Uhn CHA, Hyun-Joong KIM