Abstract: A memory device includes a load circuit, one or more reference voltage generators, a voltage regulator, and a clamp circuit. The one or more reference voltage generators are configured to generate an internal power reference voltage. The voltage regulator is configured to generate an internal voltage based on the internal power reference voltage and supply the generated internal voltage to the load circuit. The clamp circuit is configured to control a level of the internal voltage.

Abstract: An operation method of an unselected read voltage generator included in a non-volatile memory device includes applying a first voltage to a first word line group and a second word line group of unselected word lines among a plurality of word lines connected to a plurality of memory cells during a first time, floating the first word line group and applying a second voltage to the second word line group during a second time, and floating the second word line group and applying the first voltage to the first word line group during a third time. The unselected read voltage generator includes one voltage regulator that generates the first voltage based on a first reference voltage and generates the second voltage based on a second reference voltage.

Abstract: A semiconductor device includes first lower electrode lines and second lower electrode lines provided on a substrate and disposed alternately in a direction that is parallel to an upper surface of the substrate; a first interlayer dielectric; first upper electrode lines and second upper electrode lines provided on the first interlayer dielectric and disposed alternately in the direction, at least one of the first upper electrode lines overlapping in the vertical direction with one of the first lower electrode lines, and at least another of the first upper electrode lines overlapping in the vertical direction with one of the second lower electrode lines; and a via line provided between the at least one first upper electrode line and the first lower electrode line that are in the vertical direction overlapping each other, the via line extending through the first interlayer dielectric.

Abstract: Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells, and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit including a first pump block, a second pump block, and a common pump block. The voltage generating circuit connects the first pump block and the common pump block in parallel to generate a first operating voltage among the plurality of operating voltages and connects the common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages. The common pump block is configurable to match the first pump block, the second pump block, or both, as needed.

Abstract: A memory device includes a plurality of internal circuits, and an internal power generating circuit electrically coupled to the plurality of internal circuits. The internal power generating circuit is configured to: (i) generate a standby reference voltage based on an external supply power signal, and supply a standby internal power signal generated in response to the standby reference voltage to the plurality of internal circuits during a standby mode, and (ii) generate a plurality of active reference voltages based on the external supply power signal, and supply each of a plurality of active internal power signals generated in response to respective ones of the plurality of active reference voltages to corresponding ones of the plurality of internal circuits during an active mode.

Abstract: A method of dividing, into a plurality of units, a glass substrate including a glass core, an upper stack stacked on a top surface of the glass core, and a lower stack stacked on a bottom surface of the glass core, includes a stack removal operation of removing an upper stack and a lower stack of a division target region along a predetermined line by using a laser, a laser perforation operation of perforating the glass core along the predetermined line by using the laser, and a physical or laser breaking operation of dividing the glass substrate on which the perforation operation is performed, into the plurality of units by using a physical or laser method.

Abstract: Disclosed in the present invention is a method for forming a precise through-hole at high speed by using an infrared laser, wherein the method irradiates in turn single modulated Bessel beam onto a workpiece in a scanning fashion by means of a mirror structure with at least one driving unit coupled to form a laser scanning processing pattern that changes the characteristics of the workpiece by precisely micromachining the workpiece into various shapes or sizes at high speed, and then wet-etching the workpiece, such that the method not only enables laser-machining the workpiece at high speed by significantly reducing laser-machining time compared to conventional methods, but also improves productivity by reducing etching time.

Abstract: Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells, and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit including a first pump block, a second pump block, and a common pump block. The voltage generating circuit connects the first pump block and the common pump block in parallel to generate a first operating voltage among the plurality of operating voltages and connects the common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages. The common pump block is configurable to match the first pump block, the second pump block, or both, as needed.

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the

Abstract: Disclosed are a method and an apparatus for converting a musical element so as to provide a vibration in an electronic device. According to various embodiments of the present invention, an electronic device may comprise: a display; a vibration generation apparatus for generating a vibration; and a processor functionally connected to the display and the vibration generation apparatus, wherein the processor is configured to: select multiple frequencies, using a musical element; set at least one vibration on the basis of the selected multiple frequencies; and generate a vibration pattern on the basis of the set vibration. Various elements are possible.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.